What do you get when you don’t run Energy Micro’s 32-bit Cortex-M3 processor (Fig. 1) at full speed (mode 0)? A very low energy bill. In most instances, this 32-bit microcontroller sips less power than ultra-low-power 8-bit microcontrollers, so why not take advantage of 32-bit performance?
Extensive clock gating within the chip design is a major factor in reducing power requirements, but so is judicious use of the different power modes and how the system is implemented. The 32-MHz EFM32 uses as little as 195 µA at 3 V and 1 MHz. In the “deep sleep” mode 4, it uses only 20 nA with a 160-µs wakeup time. Startup time for modes 2 and 3 is only 2 s.
A closer look at the peripheral complement and its relationship to the power modes reveals how designers can conserve power. Mode 4, the lowest setting, is typical with a wakeup possible via power and a transition on an I/O pin such as a button press. More active applications would operate at mode 3 where the system can wake up when an address is recognized on the I2C interface, an analog comparator transition occurs, or a timer overflows.
Mode 2 uses more power but allows the LCD to run along with the low-energy UART and I2C interface. The DMA and SRAM are active, so the serial interfaces can transfer data without starting up the processor. The low-energy peripherals are designed to use less power than the high-speed peripherals.
The peripherals also use the 32-kHz low-frequency oscillators, which lets their design be more stringent—hence, the lower power requirements. They won’t go as fast as the highspeed peripherals, so their use will be application-dependent. The low-energy UART uses 100 nA at 9600 baud. The high-speed serial interfaces can run as fast as 8 Mbits/s.
In mode 1, the Peripheral Reflex System (PRS) is operational. It’s similar to trigger systems now appearing on other microcontrollers. Some, like Cypress Semiconductor’s PSoC (see “Field-Programmable I/O Augments 8-Bit Microcontroller”), have more sophisticated peripheral interconnect systems. But the eight triggers available with the EFM32 provide more than enough control to handle a wide range of applications without processor intervention.
A typical sequence has a comparator starting a timer that in turn starts an analog-to-digital converter (ADC) capture. The DMA support for the ADC data does not use one of the triggers. The dual-channel, 12-bit ADC can also switch modes from 1 Msample/s, which uses 200 A, to 1 Ksample/s in 6-bit mode, which uses only 0.5 A.
The PRS is important for two reasons. First, it can offload the processor. Second, it enables the peripherals to run when the processor is turned off. The processor only runs in mode 0. It is very power efficient at 180 A/MHz, but maximum power conservation occurs if the processor is off more often than not. Power control of individual peripherals is possible, so the PRS often will control only a fraction of the devices at one time.
Pricing starts at $1.55. A $299 development kit uses a pair of EGM32 chips (Fig. 2). One handles energy monitoring chores with results passed back to the development PC or displayed on the LCD. The second chip can also track power utilization of the external hardware that can plug into the board’s expansion header. Either chip can drive the LCD so it can be used by the application. Keil and IAR provide development tools for the EFM32.