Electronic Design

Maintain Power-Conversion Efficiency While Saving PCB Space

Designers of portable electronics such as cell phones, portable media players, and GPS devices are always pushing to squeeze every ounce of battery life out of the application. In particular, in the realm of power conversion, engineers aspire to ensure that every coulomb that leaves the battery finds its way to a point-of-load (POL) without being lost or dissipated as heat.

The solution is not always straightforward, though, because as in most analog disciplines, multi-dimensional tradeoffs must be considered. Specifically, efficiency and footprint often seem to pull in opposite directions. However, a split-supply lowdropout regulator (LDO), such as the FAN2560, may let you have your cake and eat it, too.

Switchers have become popular for extending battery life in applications where the POL is at a voltage substantially lower than the battery supply. A typical “energy conscious” application may use two switchers to supply power to 1.8-V and 1.5-V loads (Fig. 1).

The efficiency in such a system is quite high. Assuming a battery supply (VBAT) of 3.6 V and 150 mA delivered to each load, the total power-conversion efficiency of two 3-MHz switchers with multilayer chip inductors is typically 90%. However, the tradeoff is that the application requires two inductors covering about 10 mm2.

Another solution is to use one switcher and one LDO (Fig. 2). The obvious benefit is the need for only one inductor, which consumes about 5 mm2. However, the tradeoff is a lower efficiency due to linear regulation of the second channel.

With VBAT = 3.6 V and 150 mA delivered to each load, total power-conversion efficiency is typically 60% (90% for the switcher and 42% for the LDO). Not only does this hurt functions like talk time, but the system designer also now faces thermal-dissipation issues across the LDO.

A third approach is to use an LDO with a split-supply architecture (Fig. 3). In this case, the switcher is post-regulated by an FAN2560 split-supply LDO. This device uses one supply as the input to the drain of the pass FET and the other supply to drive the gate.

In this circuit, most of the voltage drop is converted at the higher efficiency provided by the switcher, while the remaining 300 mV is converted linearly from the output of the switching regulator (V1). VBAT is used only to bias the gate and, as a result, consumes only on the order of tens of microamps. This configuration needs only one 5-mm2 inductor and achieves an overall efficiency of 83%, assuming 150 mA for each load and VBAT = 3.6 V. In addition, by having access to the VBAT line, the architecture can use an NMOS as the pass device, which typically allows for better dynamic performance in areas such as transient response.

To summarize the three scenarios:

  1. 1: Efficiency = 90%, inductor footprint = 10 mm2
  2. 2: Efficiency = 60%, inductor footprint = 5 mm2
  3. 3: Efficiency = 83%, inductor footprint = 5 mm2

The above scenarios may have been somewhat “hand waved.” However, the margin of difference between the scenarios in terms of efficiency and footprint is large enough to allow such liberties.

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