Designers can reduce the peak amplitudes of the spectral components in a pulse-width modulation (PWM) controller’s electromagnetic interference (EMI) profile by dithering the controller’s switching frequency.
Clock dithering spread-spectrum techniques aren’t meant to replace traditional EMI-lowering techniques, but they can substantially reduce the EMI profile of the system when they’re used in conjunction with traditional techniques. They also can lower costs by reducing the amount of filtering and shielding needed to pass certain emissions standards.
The results below were obtained using external spread-spectrum dithered clock sources, both dedicated ICs and FPGAs, driving a PWM buck converter. The FPGA clock source is the better choice when it is already available in the system since it eliminates the need to add additional components. A dedicated IC solution is still sometimes used for simplicity or when a suitable FPGA is not available.
To obtain the results described here, the sources were used to clock one of Exar Corporation’s PowerXR devices, all of which give designers the flexibility to select a PWM controller switching frequency and to synchronize to an external clock source that is dithered.
In a typical PWM controller, the clock waveform is a pulse train, and its frequency spectrum consists of the fundamental switching frequency, fSW, and higher-order odd harmonics (Fig. 1a). Spreading the spectrum of the fundamental switching frequency will distribute the concentrated energy contained in the fundamental frequency and the higher-order harmonics over a wider bandwidth, reducing peak emissions (Fig. 1b).
For example, if fSW = 300 kHz, the resulting higher-order harmonics would be 900 kHz, 1.5 MHz, 2.1 MHz, and so on. The amplitude of the fundamental switching frequency will be the highest, with decreasing amplitudes for the higher-order harmonics.
Externally, the amplitudes of the actual radiated components will depend upon radiation transmission efficiencies and many other factors, including the frequency, layout, and trace lengths. But the amplitudes will generally decrease as the frequency increases with maybe one or more frequencies radiating more efficiently than others.
Modulating the fundamental switching frequency between two frequency boundaries is called clock dithering. Typically, the dithering of the PWM controller’s switching frequency will vary the fundamental switching frequency over a fairly narrow range. For example, if fSW = 300 kHz, then a ±1.5% symmetrical dithering about this frequency (referred to as center-dithering) with a triangular-wave dithering function will result in a range of PWM controller switching frequencies from 295.5 kHz to 304.5 kHz.
The resulting dithered frequency spectrum shows a decrease in the amplitudes of the components as well as an increase in their individual bandwidths. There has additionally been an increase in the noise floor because the wide-band energy remains constant.
The dither frequency, fDITHER, is typically between 20 and 40 kHz. More complex modulating waveforms are possible, but it has been shown that the simple triangle waveform yields the best results. Analytically, it also has been shown that the reduction in amplitude (in dB) of the spectral components as a result of clock dithering can be expressed by:
Spectral attenuation \\[dB\\]=10*log\\[(fsw*δ)/(fDITHER/n)\\]
fSW = PWM controller switching frequency (between 300 kHz and 1.5 MHz for PowerXR devices)
δ = percentage dither about the fundamental switching frequency (typically between ±0.25% and ±5%)
fDITHER = dither modulation rate
(typically between 20 kHz and 60 kHz)
n = system clock frequency divider used by the regulator
An increase in δ has the same effect as a decrease in fDITHER.
Dedicated Spread-Spectrum Clock Generators
Several manufacturers produce dedicated IC clock dithering spread-spectrum clock generators. In a typical device, the reference clock source for the IC is either derived from an external crystal (XTAL) or an external clock source (CLKIN) (Fig. 2).
The programmable phase-locked loop (PLL) generates a clock source in the range from a few megahertz up to more than 100 MHz depending on the crystal or external clock source frequency.
Several external spread-spectrum control lines are usually available to control the range of dithering relative to the reference clock source frequency. These control lines may also determine if the clock spectrum will be center-dithered, down-dithered, or up-dithered relative to the reference-clock source frequency.
The exact range of reference frequencies supported will depend on the IC, but it usually covers a range broad enough to support the system clock frequencies required by the driver. There are also many manufacturers of crystals, so it is usually straightforward to find one close in frequency to the required system clock frequency.
For example, if the required PowerXR system clock frequency is 28.8 MHz (300-kHz PWM switching frequency), then a suitable crystal might be the Abracon ABLS-28.63636MHZ-B4-F-T. It outputs a frequency of 28.63636 MHz, which is within 0.57% of one of the acceptable PowerXR system clock frequencies: 28.8 MHz. In that case, it would also allow for a center-dithering of ±1.1% (with a comfortable margin) about the reference clock source frequency without violating the chip’s datasheet requirements.
Using Dithering FPGA Devices
A detailed treatise of how to implement a spread-spectrum clock generator using an FPGA device is beyond the scope of this discussion, but it is beneficial to provide a brief overview. Detailed information on implementing a spread-spectrum clock generator can be obtained from the FPGA manufacturer. If FPGA resources are present and available in the system, then implementation of the spread-spectrum clock generator in the FPGA can provide cost and space savings over the dedicated IC approach discussed earlier.
Consider a block diagram of a typical spread-spectrum clock generator implemented with an FPGA (Fig. 3). Most FPGA manufacturers provide spread-spectrum building blocks or primitives that can be used to generate a clock-dithered signal from a reference clock source.
The reference clock is typically derived from a divider or multiplier block and is equal in frequency to the required system clock frequency. The fine tuner block is controlled by the tuning/dithering command block and ramps the PLL output frequency (CLKOUT) up and down with configurable frequency steps and configurable time intervals between these steps.
Configuration details of the PLL core block can be obtained from the FPGA manufacturer, but the internal feedback is typically broken and the fine tuner block is placed within the external feedback loop as shown.
Interfacing The Driver
The PowerXR devices use a programmable system clock frequency and a programmable divider to generate the PWM controller switching frequency, fSW. When one of these devices is configured to operate from an external synchronizing clock source, the frequency of the source must be within ±5% of the internal system clock frequency.
The datasheet provides a table to help determine the divide-down coefficient, n. For operation at 300 kHz, for example, the clock frequency might be 28.8 MHz with an n value of 96. In this case, the calculation for spectral attenuation for δ = ±1.1%, (i.e., 2.2%), and fDITHER = 56 kHz yields:
Spectral attenuation = 10*log\\[(fSW*δ)/(fDITHER/n)\\] = 10*log\\[(300 kHz)*(0.022)/(56 kHz/96)\\] = 10.5 dB
That is, the amplitude of the fundamental in addition to all of the harmonics will be attenuated by about 10.5 dB.
In the test setup used to gather emissions data for both non-dithered and dithered clock sources, the PowerXR device synchronizes to an external clock source supplied by the clock generator block (Fig. 4). The LX node in the circuit is the measurement point for the collection of non-dithered and dithered emissions data since it contains the highest voltage peaks and all of the relevant radiated spectral components.
The data gathered at the LX node is not the actual radiated emissions data because it does not include the radiation efficiencies for each spectral component, but it can be used to compare relative levels between the non-dithered and dithered clock data. The circuit contains an RC snubber network from the LX node to ground and small resistor values in series with the gates of the high-side and low-side synchronous MOSFETs. The snubber network helps to reduce ringing at the LX node, and the series gate resistors slow down the turn-on and turn-off times of the MOSFETs (at the expense of efficiency).
The XRP7714 PowerXR device is a four-channel digital PWM buck controller, but only channel 1 was enabled and used to gather emissions data. The external synchronizing clock source comes in through one of the general-purpose I/O (GPIO) ports. An I2C interface configured using GPIO4 and GPIO5 allows programming.
PowerXR devices are configured over the I2C port using PowerArchitect development software, which is downloadable from Exar’s Web site. The device was configured for a PWM switching frequency of 300 kHz based on a system clock frequency of 28.8 MHz, as explained above.
Baseline emissions data was gathered using the 28-MHz clock source with zero spreading, and then with ±1.1% center spreading as calculated above. The range of dithered frequencies for a 28.63636-MHz ±1.1% dithered clock source was:
fmax = (28.63636 MHz)(1.011)/n = (28.63636 MHz)(1.011)/96 = 301.6 kHz
fnom = 28.63636 MHz/n = 28.63636 MHz/96 = 298.3 kHz
fmin = (28.63636 MHz)(1 – 0.011)/n = (28.63636 MHz)(1 – 0.011)/96 = 295.0 kHz
The measured data represents a frequency spreading of +1.07%/–1.01% (2.08%), which is in very close agreement with the expected spread of ±1.1% (2.2%). The baseline frequency was measured as fnom = 298.3 kHz as expected. The duty cycles of each waveform are about 50%, as predicted by the voltage conversion ratio of VOUT1/VIN = 5 V/10 V = 0.5.
Overlaying the measurements in the frequency domain provides more information (Fig. 5). The frequencies lie between 6.50 and 9.00 MHz. The limitations of the oscilloscope’s noise floor capabilities prevent accurate measurements at higher frequencies, but these plots serve as good representations of the expected behavior at other frequencies.
The fast Fourier transform (FFT) function built into the oscilloscope has limitations and results in some distortions of the amplitudes, widths, and overall shapes of the frequency spectrum components, but it still serves to illustrate the advantages of the frequency dithering technique very well.
The amplitudes of all of the dithered frequency spectral components are significantly lower than the corresponding baseline components. Their widths are also slightly greater. The overall noise floor of the dithered spectrum is slightly higher as well, but the limitations of the oscilloscope’s noise floor capabilities prevent this from being seen in these plots.
The low-amplitude spectral components that are between the larger main spectral components are the result of the duty cycle not being exactly 50%. When a time domain pulse train has a duty cycle of exactly 50%, the resulting higher-order spectral components are odd multiples of the fundamental frequency, and for duty cycles other than 50%, the resulting spectral components are integer multiples of the fundamental frequency.