Electronic Design

Multiple Factors Trigger Cable Discharge Events In Ethernet LANs

Unless its causes and cures are understood, electric-charge buildup on LAN cables can result in system failures.

Network equipment designers are challenged to continually improve system performance while maintaining robust environmental performance. In particular, the convergence of the wide area network (WAN) with the local area network (LAN) has created the need for carrier-class Ethernet equipment. Considerations for Ethernet performance include such parameters as line length, return loss, and bit error rate. Equally important for minimizing network downtime is the robustness of the system to environmental hazards like electrostatic discharge (ESD), electromagnetic interference (EMI), and cable discharge event (CDE).

CDE is a real issue that requires recognition at all levels in the networking industry. This phenomenon should be differentiated and considered separately from electrostatic discharge. The characteristics of twisted-pair cable and knowledge of its environment play an important role in understanding CDE. The frequently changing cable environment also adds to the challenge of preventing CDE damage. With an understanding of its characteristics and waveforms, a system designer can maximize protection against CDE through good layout practices and a careful selection of components. Although a standard CDE test is possible in the future, current testing for CDE relies on individual interpretation. Obviously, there's still much more to learn about CDE, but awareness of it is higher than ever and solutions to protect against it are now available. At all levels, developers should be asking the right questions to ensure that their products are robust to CDE.

Damage from CDE can strike LANs when a charged twisted-pair cable connects to an Ethernet port of lower potential, commonly through an 8-pin RJ-45 connector. When the charged cable is connected, the ensuing high-energy discharge may damage the connector, the transformer circuit, or the Ethernet transceiver. In catastrophic cases, the result can be electrical overstress (EOS) to the transceiver IC caused by latch-up. Section 14.7.2 of the IEEE-802.3 specification warns of the CDE phenomenon, providing a cautionary note on possible system damage by static-charge buildup and high-energy transients on LAN cables.

Charge accumulates on cables primarily through triboelectric (friction) effects or induction. For example, as a cable is dragged across carpet or through conduit, the friction will result in an accumulated charge. Even the movement of air across a cable or movement of the cable itself causes a triboelectric charge buildup. Induction effects can be observed when cables accumulate charge from adjacent electromagnetic fields, such as light ballasts. Frequently, large triboelectric charges are seen in new installations, where unterminated cables are dragged through conduit. Newer types of cable, like enhanced category-5 or category-6, have very low leakage and will retain charge for long periods of time. Current LAN networks are highly flexible, with more incidents of disconnections and reconnections. All of these factors contribute to the increased occurrence of CDE in LANs.

Presently, the semiconductor industry has standard methodologies for testing the durability of a device or system to transient conditions. Some conditions, though, still lack tests. The standard tests for ESD are the human body model (HBM) and machine model, with most suppliers compliant to the HBM as defined by MIL Std. 883E, Method 3015.7. To determine susceptibility to latch-up, most suppliers comply with JEDEC Std. 17.

Semiconductor makers are looking into developing standard tests for charged devices, using a charged-device model. This is an ESD damage model in which the device is charged by improper handling or packaging and then discharged by a sudden connection to ground. No standard CDE tests for semiconductor devices or for equipment in the field exist, but interest for such tests is growing.

CDE Basics
The behavior and characteristics of twisted-pair cables are essential to understanding CDE. A twisted-pair cable behaves like a capacitor, as a storing charge. Physically, the capacitor forms when the cable's conductors act as one plate, earth ground assumes the role of the other plate, and the cable's insulation acts as the dielectric. Clearly, many variables influence the characteristics of this capacitor. Studies have proven that several hundred volts of charge can accumulate on an unterminated twisted-pair cable. Plus, a fully discharged cable can build up half of its potential charge within one hour.

Once charged, a high-grade cable can retain most of its charge for more than 24 hours. How different lengths of a category-5 cable can charge up over time is illustrated in Figure 1. Because longer cables have the capacity to store more charge, extra CDE precautions should be taken with systems that have cable lengths greater than 60 m.

Note how cable charge over time will vary as conditions in the environment change. For example, lower-quality cables with higher leakage won't retain charge as well as high-quality category-5 and category-6 cables. Therefore, they have fewer incidents of destructive CDE. Also, spooled cable charges up slower and won't retain charge as well as unspooled cable. Furthermore, factors in the environment, including airflow and air quality (humidity), proximity to electric fields, and cable movements, can influence the accumulation of charge on a cable. When analyzing CDE, all of these issues must be taken into account.

Another important factor to understand is the CDE waveform. Preliminary studies reveal that it can have wide variations in characteristics. Yet in general terms, the CDE waveform has high energy and exhibits both voltage and current drive. The waveform is spread out in time over hundreds of nanoseconds with rapid polarity reversals (Fig. 2). Some CDE waveforms have instead been measured in seconds of time.

In contrast, the HBM ESD event, though much higher in voltage, is lower in energy and current-limited by a 1.5-kΩ resistor. And, it has a fast unipolar pulse. The single-ended, differential images of a destructive CDE waveform at the transmitter pins of an Ethernet transceiver physical-layer (PHY) device, after a 25-ft. twisted-pair cable was charged to 1.5 kV, are captured by Figure 2. Note the occurrence of a 64.8-V transition from positive to negative voltage on the differential waveform. Also, over 600 ns of time elapses during the event. In this experiment, the PHY's transmitter was destroyed and unable to transmit packets on the network. Other experiments have resulted in electrical overstress to the PHY due to CDE-induced latch-up.

Failure analysis of PHYs destroyed by CDE reveal that the damage to silicon can be similar to ESD-induced failures. A typical analysis of damaged silicon reveals punch-through from drain to substrate in the transceiver circuit and might also exhibit arc-over from source to drain, rendering the transceiver inoperable. Additionally, an EOS condition can result from latch-up, an event induced by sufficient current or voltage injection into the circuit to create a parasitic silicon controlled rectifier (SCR) between power and ground. In other words, the CDE event can cause the PHY to latch up, which inflicts catastrophic EOS on the device.

Another study of CDE using repetitive testing reveals the CDE signature as seen by the Ethernet PHY (Fig. 3). Here, the Ethernet system was subjected to 25 occurrences of CDE where 25 ft. of category-5 cable was repeatedly charged to 750 V. This study shows that CDE is repeatable in a stable environment. The CDE signature can take on variations as conditions in the environment change.

There are several methods to reduce or prevent the effects of CDE. From an end-user's viewpoint, CDE can be prevented or avoided by appropriately handling the field equipment. For instance, a twisted-pair cable could be properly discharged before it is connected to system equipment by implementing a "brush" of ground pins into a resistor to ground. In support of CDE prevention and protection, IEEE 802.3, Section 14.7.2 states that "Such electrical safety hazards must be avoided or appropriately protected against for proper network installation and performance."

From the perspective of the board-level designer, Ethernet systems should be designed and laid out with attention paid to CDE and a focus placed on diverting energy away from IC devices. Many design elements can impact CDE performance, often with a tradeoff in system cost or performance. System design considerations include the addition of transient-voltage-suppression (TVS) diodes and the transformer circuit. Similar to zener diodes, TVS diodes are designed to clamp at a specific voltage. Specifically, TVS diodes are designed for low capacitance and a rapid breakdown above the clamping voltage. They're connected across the transmit and receive pairs, so any differences across the pairs will tend to be equalized. Therefore, TVS diodes supply protection from differential transients. Magnetics with integrated TVS diodes are an option too.

The transformer circuit will primarily help defend against common-mode transients. High-energy transients should have a pathway to ground. A recommended approach is to connect an ESD capacitor (2-kV rating) from the line-side center-tap to chassis ground. Inductance in the traces can result in high voltage that could reach the IC via other pathways, so this pathway should be kept short and direct. A chassis ground, separate from signal ground, is important too. This is because energy reaching signal ground is injected into the IC devices.

Aside from design and layout considerations, the temperature of the IC devices in the system has to be taken into account as CMOS devices are more susceptible to CDE-induced latch-up at high temperatures. Air movement across the ICs is one consideration, although most of a device's cooling occurs via its pins into the printed-circuit board. Therefore, leaving sufficient space around ICs will let them run cooler. Overall, there are many board-level considerations that will enable users to avoid CDE affects.

The design of the Ethernet transceiver IC is critical. Studies confirm that adding an epitaxial layer (Epi) to the wafer of a transceiver device improves the robustness of the device to latch-up, which can make the device more robust to CDE. The addition of Epi changes the resistance of the device's substrate, thereby reducing the forward-bias gain of transistors in the device. Epi has the effect of lessening the likelihood of a parasitic SCR formation. But, the effects of Epi on ESD immunity and jitter performance must also be considered. Typically, an evaluation of Epi and nonEpi devices results in a performance compromise.

Another factor to think about regarding ICs is geometry scaling. As geometries shrink, three things happen: the parasitic capacitance per unit area increases; smaller vertical dimensions intensify the E-fields that reduce punch-through voltages; and breakdown voltages are reduced. To offset these negative effects, IC designers must carefully implement certain design rules: choose a substrate methodology; ensure uniformity in device layout and metallization; intelligently use implants, physical placement, and spacing; and practice circuit techniques like soft ties and a balance between parallel and stacked devices. By applying these design practices and techniques, engineers can achieve a transceiver design that's robust to CDE.

Board-Level Analysis
The objective of board-level analysis is to compare CDE robustness among Ethernet systems with similar functionality. Review the test setup and procedure used in Figure 4. For each device tested, an unterminated category-6 cable was charged in 500-V increments starting at 1 kV. A transceiver was "failed" if its transmit signal amplitude degraded by more than 10%, it was unable to link, or it experienced destructive latch-up.

All systems in this analysis used the same single-port PHY transceiver (LXT970QC). The results show the failure ranges for each of the four systems tested (Fig. 5). System D on average offered a 75% better CDE performance than systems A and B. An analysis of system D revealed that the ICs in the system were spaced further apart and thus ran cooler. Another important factor was the type of magnetics used. System D employed multiple single transformers, whereas systems A and B implemented fewer quad-packaged transformers. It's believed that cross coupling of the CDE transient in the quad magnetics exacerbated the problem and led the transceiver to fail sooner.

A second device-level analysis was performed to compare the effects of IC design and process techniques on the CDE performance of Ethernet transceivers. The same testing methodology and failure criteria were used here. The devices were tested in standard evaluation boards to a minimum point of failure over 25 ft. of category-6 twisted-pair cable (Fig. 6).

The LXT970, a single-port transceiver using 0.6-µm technology, has a minimum failure point of 1.5 kV, but it shows double that with the addition of an epitaxial layer. Similarly, the LXT974A, a four-port transceiver utilizing 0.6-µm technology, experiences such a CDE performance improvement (from 1.5 to 3 kV) with a redesign of the LXT974B twisted-pair port pads.

System providers typically set the minimum acceptable limit of failure between 1 and 3 kV, as shown by the yellow shaded region in Figure 6. The LXT9763 is a newer six-port transceiver in 0.35-µm technology using design techniques to counter the effects of CDE, as well as an epitaxial layer. This resulted in 5 kV, a performance increase of 3.3 times that of the first units tested, well above the minimum acceptable limit. This study clearly illustrates how the effects of CDE can be minimized through IC design, and that the selection of ICs is key when designing an Ethernet system.

Acknowledgement:
The authors wish to thank Roger Karam, signal integrity engineer, Cisco Systems, Santa Clara, Calif., for his help and advice in the preparation of this article.

John Deatherage is a product marketing manager for Intel's PHY products in the company's Network Components division, Sacramento, Calif. He holds a BSEE degree from the University of Texas at Austin. Deatherage can be contacted by phone at (916) 854-2861, or via e-mail at [email protected]

David Jones is the applications engineer for Gigabit products in Intel's Network Components division, Sacramento, Calif. He earned his BSEE degree from the University of California at Sacramento. Jones can be reached by phone at (916) 854-2950, or through e-mail at [email protected]

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