Engineers who design products that plug into the ac mains face upcoming efficiency mandates that will make power-supply design tougher—and, one hopes, more lucrative. To some extent, the same is true for designers of portable equipment, as consumers get used to ever more powerdraining features while simultaneously demanding equal or longer battery life.
Back in the 1990s, the Environmental Protection Agency (EPA) created a voluntary labeling program called Energy Star, which only addressed sleep mode. It was a first step, but since it was voluntary and ignored operational efficiency, it had modest impact.
Focusing on operational efficiency in personal computers, Ecos Consulting partnered with a group of electric utilities to create another voluntary program called 80 Plus. The name of the program signifies a requirement for 80% or better efficiency at 20%, 50%, and 100% of rated load, plus a power factor greater than 0.9 at rated load.
Manufacturers of desktop computers and desktop-derived servers earn $5 and $10 rebates, respectively, for every unit with a certified power supply sold in participating utilities’ territories. Also, even though 80 Plus is voluntary, U.S. government
agencies will pay a premium for 80 Plus-qualified computers. In the past, efficiency curves tended to show a pronounced hump at slightly less than maximum design load, with a severe droop—even down as far as 40% or 50%—at low current demands. Yet many applications spend days just idling and far less time drawing peak power. The 80 Plus initiative aims at reducing total wasted watt-hours, not just optimizing efficiency at one point on the curve. Figure 1 demonstrates the kind of success that is possible.
Last July, the EPA incorporated 80 Plus into a revised Energy Star computer specification. The EPA also revised the Energy Star specification for laptop adapters, mobile phones, printers, scanners, digital cameras, and other appliances. Similar programs that harmonized with Energy Star exist in other countries, including Japan, China, and the nations of the European Union.
Although these programs are still voluntary, the U.S. and other countries are considering mandatory standards for power-supply efficiency. For example, the Energy Policy and Conservation Act (EPCA) directed the U.S. Department of Energy to determine by August 8, 2008 whether energy conservation standards shall be developed for battery chargers and external power supplies.
Meanwhile, the California Energy Commission’s mandatory Appliance Efficiency Regulations (CEC-400) include new Energy Star requirements for external power supplies. And that’s where the bite comes. Nobody would consider building a new electronic product they couldn’t sell (or even warehouse) in California, yet that’s what’s exacted by CEC-400.
Paralleling global efficiency requirements are mandated limits on power factor—effectively the harmonics of switching- regulator frequencies placed on utility lines. “Crossing the threshold of 75 W input has significant consequences. In effect, 75 W is the power threshold beyond which EU regulation (IEC1000-3-2) for the reduction of harmonic currents applies to class D electrical equipments,” explains the reference design notes from a few years ago for an ON Semiconductor notebook acdc adapter.
The notes also state that “notebook adapters are classified under class D. This regulation stipulates the maximum level of harmonic currents that class D equipment can inject on the mains ac line. The IEC1000-3-2 regulation is currently mandatory in Europe and Japan. In a sense, the mobile/global nature of the notebook adapters make them the first mass-market power supply to fall under the IEC1000-3-2 target.”
THE ENGINEERING PROBLEM
Turning f rom regulation to design approaches that meet those regulations, consider the drags on efficiency in a basic step-down (buck) voltage regulator. Allowing for circuit differences, there are parallels in all switching-regulator topologies.
In a basic, non-synchronous buck-regulator circuit, the forward-voltage drop across the low-side rectifier diode is in series with the output voltage, so its losses seriously impact efficiency (Fig. 2). “Even at 3.3 V, rectifier loss is significant,” points out Maxim Appnote AN652. “For step-down regulators with a 3.3-V output and a 12-V battery input, the 0.4-V forward voltage of a Schottky diode represents a typical efficiency penalty of about 12%, aside from other loss mechanisms,” the note says. The situation only gets worse at the lower regulator output voltages required by the latest processors and FPGAs.
Synchronous rectification—essentially replacing the diode with a switch, usually another MOSFET—improves powerconversion efficiency. Appnote AN652 goes on to say that “For an input voltage of 7.2 V and an output of 3.3 V, a synchronous rectifier improves on the Schottky diode rectifier’s efficiency by around 4%.”
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Explicitly, as output voltages shrink to match the needs of smaller-geometry ICs, the voltage drop across RDS(ON) becomes more and more significant. In addition, the power needed to drive the MOSFET gate cancels out some of the efficiency gained from a reduced forward-voltage drop.
Another efficiency limitation arises from dead-time delay, inserted by the synchronous controller to prevent “shootthrough,” or the switching overlap of the high-side and low-side MOSFETs that could have both conducting simultaneously. During this dead time, the low-side MOSFET’s parasitic body diode would generally act as a clamp on the negative inductor voltage swing.
However, the body diode is lossy and slow to turn off, which could result in a 1% to 2% efficiency penalty. Therefore, some designers parallel the lower MOSFET with a Schottky diode, which turns on at a lower voltage than the body diode.
Even with that kind of design, conduction losses during the dead time can become significant at high switching frequencies and especially at light loads. When load current is light, the current in the switching supply’s inductor discharges to zero. In that case, the power-supply designer has several options.
From a simplicity standpoint, it’s attractive to drive the lower MOSFET gate with the complement of the signal on the upper MOSFET’s gate. Alternatively, the switching controller could continue to hold the synchronous switch on until the beginning of the next cycle.
In that case, when the inductor current would start to flow in the reverse direction, the regulator’s controller could sense the inductor current’s zero crossing in each cycle. Then it either shuts off the synchronous rectifier or simply disables the synchronous rectifier at light loads.
Many advantages are possible when holding the synchronous switch off until the beginning of the next cycle. But there’s also at least one drawback in terms of efficiency. When the inductor current reverses, the synchronous rectifier pulls current from the output, storing the energy in the input bypass capacitor and replacing the lost output energy during the next half cycle. This dissipates power in all of the circuit’s parasitic resistances and switching inefficiencies.
One workaround has been pulse-skipping. The supply reverts to non-synchronous operation, with the Schottky doing the commutation. That re-introduces the diode drop as a drag on efficiency. The most efficient approach—and the most complex in terms of design—uses zero-crossing detection, or “valley control” (explained below).
Those are some of the essential limitations of older designs and some traditional ways of dealing with them. Next, let’s look at some of the most recent power-supply products that attempt to flatten the efficiency curve across all load regimes—and largely succeed in doing so.
One of the companies longest associated with power-supply efficiency, Power Integrations, introduced its EcoSmart technology in 2002 as part of its LinkSwitch LNK501, a 3-W constant-voltage/ constant-current (CV/CC) ac-dc switcher for portable devices. This development illustrated some new thinking (Fig. 3).
Traditional switching supplies placed the switching element on the low side of the transformer. But the LNK501 places it on the high side. Referencing the IC to the rectified dc input made it possible to derive all feedback information for an approximate constant-voltage and constant-current operation from the primary- side clamp circuit. Removing the sense resistor, along with the rest of the secondary-side current-sense circuit, cut secondary loss and increased efficiency by about 10%.
After a bootstrapping startup, the primary-side leakage inductance clamp (D5 and C4) provides power for the LNK501. The clamp is also the source for feedback information—that is, the voltage developed across C4 is an approximate representation of the output voltage transformed through the transformer turns ratio. Resistor R1 converts this reflected voltage to a current that’s applied to the IC’s control pin.
The operating modes are discontinuous flyback with voltage-mode control for the constant-voltage portion and current-limit operation for the constant-current portion of the output characteristic. Once the output voltage reaches regulation, control of the output transitions to constant voltage. If the output load increases beyond the peak power point and the output voltage falls, the reduced control-pin current lowers the internal current limit, providing an approximate constant-current output characteristic.
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Under normal load conditions, when the control current exceeds a predetermined value, the duty cycle is controlled, providing an approximate constant-voltage characteristic. For light-load/ no-load conditions, when the duty cycle drops below 3%, the switching frequency is reduced to cut energy consumption.
With that CV/CC output characteristic, the flyback transformer is always in discontinuous current mode (DCM). DCM is another way of saying that current, and thus the magnetic field in the coil, may reach or cross zero. With DCM, all of the energy is delivered to the load during the MOSFET off time for each switching cycle. (In continuous-current mode, current and the magnetic field never reach zero.)
Over the years since it introduced the LNK501, Power Integrations has made the improvement of power efficiency across all ranges of power output and load conditions into a crusade. Last year, the company upgraded its higher-power (48 W sans heatsink, 150 W with heatsink) TOPSwitch ac-dc line with the HX series. The TOPSwitch HX chips are monolithic ICs that integrate a 700-V power MOSFET with a controller and supervisory functions.
No-load power consumption for HX parts is less than 200 mW. At higher loads, high efficiency is achieved via a multimode control scheme. At high loads, the chips use a fixed-frequency pulsewidth- modulation (PWM) control technique. As load decreases, the controller transitions to a variable-frequency mode and then to a lower fixed-frequency PWM mode that avoids audible frequencies. At very low loads, the controller transitions into a cycleskipping mode that delivers maximum power to the output for 1-W input and consumes very little power in standby.
Texas Instruments’ portfolio of switch-mode regulators is too broad to cover completely. Some of TI’s buck converters, such as the TPS51117, approach low-load efficiency by varying switching frequency. “If auto-skip mode is selected, the TPS51117 automatically reduces the switching frequency during a light load condition to maintain high efficiency,” says the TPS51117’s data sheet.
“As the output current decreases from a heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected,” it continues.
“Since the output voltage is still higher than the reference at this moment, both high-side and low-side MOSFETs are turned off and wait for the next cycle. As the load current decreases further, the converter runs in discontinuous conduction mode, taking longer time to discharge the output capacitor below the reference voltage. Note the ON time is kept the same as during the heavy load condition,” the datasheet says.
“In reverse, when the output current increases from a light load to a heavy load, the switching frequency increases to the preset value as the inductor current reaches... continuous conduction,” it concludes.
Another chip, TI’s eight-pin UCC28600 quasi-resonant, flyback green-mode controller, incorporates three control modes: quasi-resonant/DCM mode, frequency-foldback mode, and “green mode.” Quasi-resonant (QR) and DCM operation occur for high loads, since the rising edge of the gate drive to the switching MOSFET always occurs at the valley of the resonant ring after demagnetization (resonant valley switching).
Resonant valley switching is also imposed at maximum switching frequency. In frequency-foldback mode, the voltage-controlled oscillator is restricted to 40 to 130 kHz. At the lightest loads, green mode maintains the oscillator at 40 kHz, and switching enters a hysteretic “burst” or “hiccup” state.
National Semicondcutor’s LM26480 embodies its own forms of synchronous switching frequency control in a multi-output controller. It contains two high-current, step-down dc-dc converters and a pair of linear regulators. The chips are for portable systems running off lithium-ion batteries.
One of the buck regulators can provide any voltage between 0.8 and 2.0 V at up to 1.5 A. The other supports 1.0- to 3.3-V output levels, also up to 1.5 A. The low-dropout regulators (LDOs) can be set to output between 1.0 and 3.5 V, with ±3% accuracy at up to 300 mA with 25-mV (typical) dropout.
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The switching regulator efficiency across the load range is remarkably flat (Fig. 4). There are three modes of operation: PWM, pulse-frequency modulation (PFM), and shutdown. PWM is for loads of approximately 70 mA or higher. Lighter loads cause the device to automatically switch into PFM. That cuts the IC’s quiescent current to around 15 µA.
Each buck converter has a switching P-channel FET and a synchronous rectifying N-channel FET. During PWM operation, the converter operates as a voltage- mode controller with input-voltage feed-forward.
At very light loads, PFM mode means reduced switching frequency and supply current. The transition occurs if either the inductor current becomes discontinuous or if the peak P-channel switch current drops below a certain level, roughly 66 mA + VIN/160 O.
Here’s the interesting part. During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation. This allows more headroom for voltage drop during a load transient from light to heavy load.
Explicitly, the controller monitors the output voltage and controls the switching of the output FETs so that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the “high” PFM comparator threshold, the P-channel MOS power switch turns on.
It remains on until the output voltage exceeds the “high” PFM threshold or the peak current exceeds another preset level, this time roughly 66 mA + VIN/80 O. Once the P-channel MOS power switch is turned off, the N-channel MOS power switch turns on until the inductor current ramps to zero.
Now for the power savings. Once that N-channel MOS zero-current condition is detected, that switch is turned off. If the output voltage falls below the “high” PFM comparator threshold, the P-channel MOS switch is again turned on and the cycle repeats until the output reaches the desired level. Once the output reaches the “high” PFM threshold, the N-channel MOS switch is turned on briefly to ramp the inductor current to zero. Then, both output switches are turned off and the part enters an extremely low power mode.
The quiescent supply current during this “sleep” mode is less than 30 µA. When the output drops below the “low” PFM threshold, the cycle repeats to restore the output voltage to roughly 1.6% above the nominal PWM output voltage. If the load current increases during PFM mode, causing the output voltage to fall below the “low2” PFM threshold, the part transitions into fixed-frequency PWM mode.
Consider Zilker Labs’ ZL2004 and ZL2006 point-of-load (POL) regulators, introduced last January. Following on the company’s first product, the ZL2005, they combine a number of circuit techniques to maximize efficiency across the parts’ load ranges. The ZL2006 integrates 3-A MOSFET drivers that can support loads in excess of 40 A, and there’s no need for an external driver. The ZL2004 interfaces with external driver/MOSFET ICs and power-train modules.
The ZL2006 and ZL2004 use adaptive dead-time control, something included in the earlier ZL2005s. A proprietary technology dynamically adjusts the transition times related to turning on and off the synchronous MOSFETs.
Then there’s a new technique called “adaptive diode emulation.” As load current drops, typical synchronous stepdown converters will begin to sink current to maintain regulation. This removes energy from the output capacitor and reduces efficiency. The Zilker chips detect this transition point and prevent the lower MOSFET from turning on.
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All Zilker chips include a proprietary bus that allows multiple chips to be synchronized and operated in parallel (Fig. 5). Parallel operation helps optimize efficiency at higher loads, but the higher losses associated with switching more components can result in lower efficiency when the load current is reduced.
The ZL2006 and ZL2004 add the ability to automatically shed phases in response to drops in load current. The dropped phases can then be re-enabled when the load current is again increased. And like other chips, the ZL2006 and ZL2004 can reduce their operating frequency within a pre-defined range due to load current changes.
Uniquely, the new Zilker POLs provide what the company calls adaptive compensation. It’s necessary to compensate a regulator’s control loop to get the optimum tradeoff between fast transient response and stability across the operating range. The new chips can dynamically modify the loop-compensation coefficients in response to varying load conditions, without a need for external components to set or vary the loop compensation.
For the latest on regulations, I am indebted to power-industry guru Lazar Rozenblat for his recent blog at http://smps-power.blogspot.com, “Power Supply Efficiency Increase: Requirements and Trends.”