As logic designs have migrated from 5- to 3.3-V levels, oscillator manufacturers have responded by introducing new products for the lower supply voltage. In addition to the basic crystal-controlled clock oscillators, voltage-controlled (VCXOs) and temperature-compensated (TCXOs) versions operate at 3.3 V. But demands for lower power consumption, faster clock rates, and finer transistor geometries continue to push high-performance chips to lower values of VCC. With ASICs currently being designed for 2.5- and 1.8-V operation, oscillator vendors are beginning to develop devices to operate at these voltages.
For the most part, developing basic crystal-controlled clocks that can run off of 2.5 or 1.8 V is straightforward, relying on the same circuit architectures used at higher voltages. Demands for tiny surface-mount packaging, though, complicate the low-voltage design for oscillator makers. Meanwhile, testing the devices can become more difficult for the oscillator user (or the system designer).
More serious challenges arise when the oscillator in question isn't a simple clock, but rather a VCXO. In this case, lower supply values lead to a limited control-voltage range that either restricts VCXO performance or else imposes a design burden on the oscillator designer or the oscillator user.
To date, several low-voltage oscillators have been introduced. Others are expected to follow shortly. These products are likely to be 3.3-V designs that have been requalified at 2.5 V. Nevertheless, as customers increase their requests for lower supply voltages, vendors should start ramping up the development of oscillators specifically built for 2.5 V, 1.8 V, and other low values.
Many key oscillator performance parameters, such as stability and jitter, are essentially unaffected by supply voltage. Instead, oscillator startup is a concern. This factor depends more on the vendor's selection of a crystal than on the design of the oscillator circuit.
More precisely, starting oscillation at lower voltage calls for a crystal with lower equivalent series resistance (ESR). Unfortunately, this conflicts with the demand for small package size—as the crystal gets smaller, ESR rises. Designers may have to compensate for the higher resistance in the oscillator circuit. "Normally, the crystal starts from thermal noise," says David Babcock, chief engineer at Cardinal Components. "But at 2.5 V and lower, you may have to hit the crystal with a burst of energy to start it."
Ramon Cerda, applications engineer at Raltron Electronics, explains that the issue of the crystal's ESR will make it harder to build oscillators at 1.8 V while still satisfying demands for tiny surface-mount packaging, which is shrinking from the already small 5- by 7-mm outline. With handset manufacturers driving market requirements, Cerda says, "The challenge right now is to go to 3.2 by 5 mm." For companies like Raltron, which already is shipping 2.5-V clock oscillators and plans to release 1.8-V SMD versions by year's end, packaging is an immediate concern.
If a customer requests a 1.8-V oscillator but will accept a larger package style, Raltron can readily build it using discrete components. But very small surface-mount versions are another matter, as they require an ASIC for the circuitry. Consequently, oscillator vendors have to develop new chips to accommodate surface-mount packages. Cerda notes that one of the goals in designing the lower-voltage ASICs will be to make them 3.3-, 2.5-, and 1.8-V compatible without compromising their performance at the lowest supply voltage.
Will Work At More Than One Voltage
Another vendor, MF Electronics, concurs that lower-voltage oscillator ASICs will work over a range of values. Company president Marty Finkelstein says, "If we design an ASIC to run on 2.5 V, it will run on 1.8 V as well." He also notes that the company's oscillators currently operate off of 3.3 V, yet will run on 2.5 V. This wouldn't be considered an optimum solution, but rather a temporary fix until the development of new silicon.
George Maronich, president and chief technology officer at Frequency Management, points out that many of the commercially available oscillator ICs de-signed for fundamental-mode operation at 3.3 V generally have no problem operating at 2.5 V. They will start up at voltages as low as 1.9 V. On the other hand, those 3.3-V ICs designed for third-overtone oscillation tend to perform marginally—if at all—at 2.5 V, depending on their tuning and gain characteristics.
Engineers should note, though, that it's up to the oscillator vendor to determine whether an existing oscillator is suitable for operation at 2.5 V. Users should not run a 5- or 3.3-V oscillator at 2.5 V or lower without first consulting the manufacturer. To do so risks the device's performance. In fact, lowering the supply voltage may change the oscillator's operating frequency as well as other parameters, such as duty cycle.
The suitability of existing ASICs for 2.5-V operation is reflected in some early introductions of oscillators designed for this supply level (see the table at www.PlanetEE.com). In some cases, vendors simply requalified devices built for 3.3 V at 2.5 V. Pletronics, a vendor focusing on high-speed networking applications, has been shipping 2.5-V oscillators using the same silicon developed for 3.3 V. But building the 1.8-V 70-MHz+ clock that it's now developing required a chip redesign.
Meanwhile, SaRonix has already introduced a 1.8-V HCMOS clock oscillator to the marketplace. Originally developed as a custom unit, the vendor's DIP-style NTH series and surface-mount S1612 series generate outputs in the 20- to 70-MHz range (see the table, again).
According to Beat Kocher, director of marketing and business development at SaRonix, "Many of the boards that use 1.8-V devices are mixed-device boards," with 1.8-, 2.4-, and 3.3-V logic all together. Now, these designs probably implement 3.3-V oscillators with level translators. But as the lower voltages become more common, Kocher believes that designers will request lower-voltage oscillators.
Using the 1.8-V and 3.3-V oscillators shouldn't differ much. Because of the part's limited frequency range, board layout and power-supply bypassing aren't expected to change. According to Kocher, these become greater issues at 100 MHz and above. The traces that carry the oscillator output should then be treated as transmission lines and be properly terminated.
Nevertheless, even at the relatively low frequencies generated by SaRonix's new oscillator, some minor performance issues arise. One is a reduced drive capability versus the company's existing 3.3-V oscillators. The maximum load for the 1.8-V devices is 15 pF, while for the company's 3.3-V oscillators, this value is 30 pF, and for the 5-V models, it's 50 pF. But the lower-voltage part has reduced power consumption.
In addition to lowering power, lower-voltage operation can reduce the noise generated by the oscillator. Maronich says the overshoot present on the leading edge of the oscillator output decreases dramatically as supply voltages drop to 2.5 V. He claims the overshoot may amount to 10% in a 5-V oscillator yet be a mere 2% to 3% in a 2.5-V version.
Even so, measuring overshoot is not a trivial matter. As Maronich points out, overshoot and overshoot-related noise are very sensitive to oscillator loading. Good RF termination techniques are critical for optimum noise performance and for certain other parameters, such as rise and fall times, and to a lesser degree, duty cycle. To measure these parameters accurately at lower supply voltages, users need to pay greater attention to their test fixtures. The contact resistance of the fixture is one concern. Oscillator users must minimize this resistance to ensure accurate readings at 2.5 V and below.
Noise Immunity A Concern
Another area for concern is the oscillator's noise immunity. While the oscillator may generate less noise at lower voltages, its immunity to external noise conducted into the oscillator on the supply lines could decrease. Finkelstein suggests that users pay greater attention to controlling power-supply noise by using proper bypassing and proper grounding techniques. Protection of clock signals as they travel across the board, particularly at the higher frequencies, might require going to differential signaling.
Naturally, reducing the VCC of the clock will affect other components involved with clock generation and distribution. At Cypress Semiconductor, producer of a variety of clocking chips, some recent product developments reflect the results of low-voltage design. In the last 12 months, it has developed a PLL chip that's compatible with a 2.5-V crystal oscillator reference. More recently, Cypress introduced clock-distribution devices with 2.5-V input and output.
Also, the company is now developing a PLL component to work with 1.8-V logic and clock signals. Ian Chen, director of operations at Cypress' Timing Technology Division, says the company is in the early stages of designing a PLL that will work with an external 1.8-V crystal oscillator to generate a 1.8-V clock for next-generation memory. This part may be introduced by late 2002.
VCXOs may pose a greater challenge in low-voltage design. As VCC drops, so does the available voltage range for controlling the oscillator's frequency deviation or pull. Given the limited control-voltage range, maintaining the VCXO's pullability becomes difficult. If migrating VCXO designs from 5 to 3.3 V was deemed tough, moving them to 2.5 V and lower should be even more so.
Maronich advises designers to think of the pullability spec as ppm/V of the control voltage. So if the supply voltage drops by 50% while other factors remain unchanged, the pullability should drop by 50%.
Still, if the customer demands the same frequency deviation range at lower supply voltages, a few options are available to oscillator designers. One approach calls for using rail-to-rail op amps to develop the VCXO's control voltage. Although these op amps cost more than standard amplifiers, they maximize the available control-voltage range, lifting some of the burden from the oscillator designer.
Another method for obtaining maximum pullability is to employ more-sensitive varactor diodes, which will provide greater frequency deviation for a given change in control voltage. Stated another way, oscillator designers will need varactors with a greater capacitance change per voltage change. Such diodes will probably cost more and add to the price of the VCXO.
Oscillator users may be able to limit the extra costs associated with high-performance varactors by lowering the pull-range specification they need. Three VCXO alternatives and the tradeoffs they incur are shown in the graphs (see the figure). In this example supplied by MF Electronics, oscillator specifiers can obtain a lowest-cost solution by accepting a reduced pullability of ±75 ppm, and by using precision op amps to supply the control voltage (see the figure, b).
A somewhat more expensive alternative would require precision op amps, but it goes a step further by specifying a pull range of ±100 ppm (see the figure, c). That value would more typically be seen at higher VCC. But the third and final implementation costs the most. It doesn't require use of the rail-to-rail op amps. Instead, the VCXO maker builds a part with the full ±100-ppm pull range while working with a control voltage range that's cut by 20% (see the figure, d).
Cerda mentions another challenge in developing VCXOs. Users expect that the pullability they obtained with VCXOs built in older, larger packages will be the same pullability they receive when they purchase VCXOs in the newer, smaller packages. Unfortunately, oscillator designers need crystals with high motional capacitance to pull the frequency. But like the low-ESR requirement, this conflicts with the need for small package size. As the oscillator packages get smaller, the crystals inside must become smaller, leading to less motional capacitance for the crystals.
Though not yet commonly available, 2.5-V VCXOs are probably the next logical step in development after 2.5-V clocks. Because pullability will become a critical issue in oscillator design, oscillator users must take a close look at their requirements before ordering. They will have to answer the question, "What is the absolute pull range (APR) required in my application?"
APR is the amount of pull range (in ppm) provided by the VCXO after the frequency errors attributed to the oscillator itself are subtracted. These errors include oscillator calibration, frequency stability, and aging. In other words, APR is the amount of frequency deviation that the oscillator can track during its operating life. For example, a VCXO with a pullability of ±100 ppm may have an APR of just ±50 ppm.
Maronich adds that designers should consider how they specify VCXO linearity, or frequency deviation versus voltage. "Engineers should be forewarned that they might have to compromise on linearity to obtain the same pull range at a lower voltage," he says. Again, the tradeoff will be linearity for cost.
Normally, VCXOs aren't specified for a linearity better than ±10%, with ±20% being standard. Yet in many applications, linearity may not be critical. So Maronich advises oscillator users to determine how much linearity they actually need, rather than automatically specifying a value that's tighter than standard. Otherwise, getting that extra linearity could require the oscillator designer to tighten up on other specs, like frequency stability, which drives up cost.
VCXO linearity is a lot like the other issues that arise in low-voltage oscillator design. They generally don't require wholesale changes in the device design, but rather more subtle changes in component selection. Despite the less dramatic nature of these changes, they suggest that system designers attain a greater understanding of their clocking needs at low supply levels to prevent overspecifying their oscillator requirements.