PoL Position

Rich Nowakowski drills down on point-of-load power-supply design techniques for performance processors.

With further integration and smaller feature sizes, processor core voltages are beginning to drop below 1V while their current consumption increases due to faster operating speeds.

The advances of process technology must be matched with point-of-load power-supply design expertise. Power-management solutions that worked in the 80s and 90s may not work well with today's performance processors. Powering a processor poses several challenges, such as the placement of bulk and bypass capacitors, inrush currents, voltage regulation accuracy, and sequencing.

BULK AND BYPASS CAPACITORS
The total current drawn by the processor is not only provided by power source itself, but also supplied by processor's bypass and the power supply's bulk capacitors. When a steep load transient occurs as a result of an abrupt change in the processor's level of activity, the instantaneous current is supplied first by the local bypass capacitors—typically small ceramic capacitors that respond quickly to changes in the load. As processing speeds increase from 500 MHz to 1GHz and beyond, the need for more energy-storing bypass capacitance becomes greater.

Another source of energy is the power supply's bulk capacitance. For newer performance processors, the bypass-capacitance requirements can be equal to or even greater than the bulk capacitance of the power supply. To avoid stability problems, care has to be taken to make sure the power supply is stable with the added bypass capacitance.

The power-supply evaluation module may work well on the bench, but not when connected to the load. Make sure the power supply's feedback loop is compensated to accommodate the additional bypass capacitance. The bulk and bypass capacitors must be close together to reduce parasitic effects.

AVOIDING SURGE CURRENTS
A power supply with large bypass capacitance poses a startup problem, since the power supply may be unable to charge a large bypass capacitor needed to meet the processor's load requirements during startup. As a result, the power supply may shut down due to an overcurrent situation, or the voltage may temporarily decrease (become monotonic) during startup, potentially causing the processor to lock up.

To reduce surge current, allow the bypass capacitors to slowly charge by increasing the startup time of the core voltage supply. Many DC-DC regulators feature an adjustable slow-start pin to extend the voltage ramp time. If the regulator doesn't have a slow-start pin, one can be implemented externally with an external MOSFET and an RC charging scheme.

Over-design of the power supply is another easy way to handle surge currents, as long as the designer can afford the size and cost penalty for the higher current rating. A DC-DC regulator with current limit is also recommended to maintain a monotonic voltage ramp up, if required by the processor.

REGULATION ACCURACY
Years ago, processors required as much as a 5% voltage tolerance. But as the process nodes continue to shrink and core voltages dip below the 1V level, tolerances become tighter and may require as little as 3% accuracy over line (operating input voltage range), load (operating output current range), and operating temperature. Please check the voltage-regulator manufacturer's guarantee in the datasheet to ensure that the regulation accuracy meets the processor's requirements. Figure 1 shows an example of the regulation accuracy of the TPS54310.

The electrical characteristics section of the datasheet guarantees performance over temperature and line conditions to 1% accuracy of the reference voltage. The load accuracy is a maximum of 0.09% at 3A. The TPS54310 can easily accommodate better than 3% over line, load, and temperature.

AC REGULATION ACCURACY
When a processor experiences an abrupt dynamic load change in a period of low-to-high activity, it quickly draws more current. This results in a voltage drop. The power supply must react quickly to the voltage changes to maintain regulation (Figure 2). The voltage spikes need to be within the voltage tolerance specifications of the processor, so be sure to check the absolute maximum core voltage requirement in the processor's datasheet.

To improve the regulation performance of a power supply during transients, reduce the inductor value to speed up the regulator's response time. Also, increase the capacitance to provide additional energy storage capability to accommodate voltage drops and spikes. It is advisable to protect the processor with a supply-voltage supervisor to provide a good power-down reset if the voltage should dip too low during a brownout.

SEQUENCING
More processor manufacturers are providing recommended timing guidelines for core and I/O power-up sequencing. Once the timing requirements are understood, an appropriate technique can be chosen by the point-of-load power-supply designer.

There are several distinct methods to power up and down a dual-power supply: sequential, simultaneous sequencing, and pre-biased startup.

Sequential sequencing can be implemented when there is a short time interval on the order of milliseconds required between the core and I/O power-up, in any order. One way to implement sequential sequencing is by simply connecting the POWERGOOD pin of one voltage regulator to the ENABLE pin of another voltage regulator.

Another method for implementing sequential sequencing is to use a hot-swap-type sequencing integrated circuit to control the turn-on and turn-off of each voltage level. This provides flexibility but consumes board space and adds cost.

Simultaneous sequencing can be used when the core and I/O voltage differential during power-up and power-down needs to be minimized. To implement simultaneous sequencing, the core and I/O voltages track each other until the lower desired voltage level is reached.

At this point, the lower voltage stops rising at its regulation point while the higher voltage continues to rise. The TPS54x80 switching regulator (with its TRACKIN pin) and the PTH series DC-DC modules (with the auto-track feature) from Texas Instruments can be used to implement simultaneous sequencing.

Figure 3 shows the core and I/O voltages tracking during power-up. When the I/O voltage is applied long before the core is to be turned "on" and a minimum delta must exist between the core and I/O voltage, pre-biasing can be easily implemented. In this case, the processor's manufacturer recommends diodes to pre-bias the core voltage before it is powered up. The voltage drops across the diodes maintain a minimum delta between the core and I/O voltages. When using a synchronous buck DC-DC converter, make sure that the low-side MOSFET is kept "off" during startup. Otherwise, the bias voltage already applied to the core will sink to ground as the DC-DC converter starts up, potentially damaging the diodes. The core voltage follows the I/O voltage by the diode voltage drop, which shows the processor's core being biased before it is turned "on." Then the core is ramped up from the biased voltage to the desired voltage level. Figure 4 shows an example of a pre-biasing startup waveform. The TPS54x73 switching regulator and the PTH series DC-DC modules can be used to implement pre-bias startup.

PROVIDING POWER TO THE PLL
Many newer processors require a separate PLL (phase-locked loop) power supply in addition to the core and I/O voltage. Executing code with an unstable PLL voltage outside of the minimum and maximum tolerance can result in corrupted data or a locked up processor. Simple precautionary measures, such as using a supply voltage supervisor (SVS), can protect the data integrity. Once the core and I/O voltages stabilize, the PLL voltage must be kept within tolerance for up to 1000 clock cycles; for example, before any code is executed. Some processors include an internal SVS function to allow the PLL voltage to settle. If your processor does not implement this function internally, use a supply voltage supervisor with a tight voltage tolerance to verify core and I/O stability. Make sure the supervisor's "RESET" time is greater than the number of clock cycles needed for the PLL voltage to settle. A low dropout regulator with a high power-supply ripple rejection (PSRR), such as the TPS79xxx family, helps reduce unwanted noise spikes into the PLL.

Today's advanced performance processors need a high-performance point-of-load power supply. Larger bypass capacitance, sequencing, inrush current, regulation accuracy, and PLL supply-voltage monitoring are today's point-of-load power-supply issues. Power-supply solutions that worked five or more years ago may not work well with newer processors. Remember that DC-DC voltage regulators are designed for specific markets and end equipment, and they have specific cost and performance targets.

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