Thanks to an embedded nonvolatile memory core, chip designers can arm themselves with a multiple-time-programmable (MTP) fuse that's manufacturable via standard CMOS logic processes. Unlike several one-time-programmable (OTP) technologies available today, the AEFuse from Impinj Inc. can be reprogrammed up to 1000 times.
The AEFuse does away with larger OTP arrays and with having to subdivide those arrays into pages. Usually, to write new data, the old page is disabled when data is written to a new replacement page. However, this approach isn't very efficient if more than a handful of page rewrites are needed. This is where an MTP solution steps in.
The AEFuse architecture offers a good solution for low-bit-count storage applications, like trim data for on-chip analog components, encryption and identification information, and chip configuration data. Organized in 8-bit banks, the AEFuse memory macro is well suited for applications requiring just 8 to 128 reprogrammable bits of nonvolatile trim and/or data storage. A single controller can support up to 16 banks (see the figure). Bit widths beyond 128 can be realized via multiple instantiations of the macro.
At the heart of the AEFuse memory lies Impinj's patented differential memory-cell design, configured so each half of a bit cell contains a separate floating gate. A logic 1 is programmed by adding charge to one side of the differential pFET cell while removing charge from the other side. A logic 0 is programmed by doing the inverse on the two sides of the cell.
This scheme can be implemented in a standard CMOS logic process (3.3-V I/O, 70-Å gate oxides). Furthermore, the AEFuse memory cell architecture exhibits a high energy barrier, which means significantly less charge leakage. The paradoxical result is that AEFuse takes full advantage of the thinner gate oxides of cutting-edge logic CMOS processes. And, by virtue of its cell architecture, it actually sees improved retention and endurance characteristics over conventional fuse approaches.
Available now, AEFuse hard intellectual-property blocks are silicon-proven and fully characterized in TSMC's 250- and 180-nm logic processes. Licensees receive physical layout files, simulation models, timing information, and all technical documentation. Users can select from over 100 configurations, including those with on-chip high-voltage blocks, oscillator, and lock bits. All configurations operate from 40°C to 125°C. Contact the company for license fees.