Implement this cost-effective voltage startup sequence for SLICs or other similar multi-rail supplies.

by Dirk Gehrke and John Betten

In this digital age, one would assume that the traditional telephone would fade out and be replaced by IP phones. However, that assumption would be wrong. Many broadbandaccess modems allow for interfacing with regular telephones, thereby providing the conversion and interface to the digital world.

Since digital subscriber service (xDSL) and cable modems eliminate the POTS (plain old telephone service) connection to the central office, these modems must handle many of the functions that would otherwise be located at the central office (CO). Functions that do need to be replicated are ringing the phone and generation of loop current for off-hook operation.

Numerous companies have developed high-voltage subscriber- line interface circuits (SLICs) that control the ring and voice transmission for these broadband access and phone systems. Some offer recommendations for applying the supply voltages to their devices in a particular sequence.

The supply voltages to a SLIC usually include several negative and/or positive voltages, depending on the end use and installation location. Larger voltages are used to ring the phone and lower voltages to power the phone while off-hook. Here, we’ll discuss a flyback converter design with a multi-tapped transformer and an inexpensive sequencing circuit setup to power up the multiple rails in a defined sequence.


Figure 1 shows a schematic of the flyback converter, in which the cost-effective UCC2813 PWM controller drives a multitapped flyback transformer. A regulated wall-brick adapter with a nominal 12Vdc output voltage provides the input voltage source.

Advantages of this design, which allows for operation over an 8V to 14V input range, include the ability to provide multiple outputs from a single power switch and control IC. The circuit operates as a discontinuous flyback. Power switch Q5 is turned on and the current increases in the transformer primary. Switch Q5 then turns off and the transformer’s energy is transferred to the secondary.

The secondary winding’s voltage increases due to the inductive kick or “flyback” of the power transformer. This voltage is reflected to the transformer secondary as a positive voltage at the anode at D1 and negative voltages at the cathode of D5 and D9.

The secondary voltage continues to increase until it reaches the output capacitor’s steady-state voltage, at which point the output diodes begin to conduct. The secondary winding current discharges to zero into the output capacitors and load resistance. The cycle then starts over again.

Output power is adjusted by varying the stored energy in the transformer primary. This is accomplished by changing the duty factor of Q5 and by the value of the load resistance. The duty-factor equation is similar to the single-winding negative flyback case. However, it’s modified by the turns-ratio of the power transformer.

The circuit implements currentmode control to improve the input line rejection and output overload protection. One key advantage to the multi-winding approach is that a single control circuit and single MOSFET can provide the multiple output voltages. The power-supply feedback loop is closed around the –51V output.

The regulation of the –27V and +60V rails are achieved by the coupling of the transformer turns between the three outputs. Very large current swings are possible on all three outputs. The –27V and –51V outputs can vary up to 200mA and the +60V can support up to 260mA. With the dc control loop closed around the –51V, its output voltage has minimal variations, primarily due to the resistive divider and reference tolerance. The +60V output voltage starts with the same tolerances. However, it incorporates the cross regulation of the transformer due to resistance and leakage inductance and varying voltage drops of its diode, and the –51V diode at different currents and temperatures.


In this particular design, the output voltage will be sequenced with the –51V applied first, followed by the +60V, and lastly the –27V. The three output voltages are derived from the transformer secondary windings (Fig. 2). Without Q1 and Q2, the output voltages would startup simultaneously. The simultaneous rise of the flyback output voltages at turn-on are shown in Figure 3. The output voltages in Figure 3 are the voltages measured at test point 1 (TP1) through TP3 in Figure 2.

Continued on Page 2

To achieve the desired startup sequence, turning on the +60V and –27V outputs must be delayed. Incorporating a P-channel FET (Q1) in series with the +60V rectified output voltage at TP1 holds off the output voltage until the –51V reaches regulation. Resistors R1 and R4 form a divider between the +60V and –51V, and are scaled so that the voltage across the gate-to-source of Q1 fully enhances the P-channel FET when both the +60V and –51V are present. The parallel combination of R1–R4 and C1 adds a programmable delay before Q1 turns on.

The component values in Figure 1 produce a delay of approximately 5 to 10ms. Since the delay is controlled by the turn-on threshold of the selected FET, some care must be taken in determining the actual range of the delay time. Zener diode D1 protects Q1 from a gate-to-source overvoltage condition, but could be deleted if desired.

Just as Q1 holds off the +60V output, Q2 holds off the –27V output. The gate of Q2 is controlled by the +60V switched output voltage. FET Q2 must be an N-channel FET, because the “trigger” voltage applied to the gate to turn it on is positivegoing rather than negativepowerdesign going, as is the case with Q1. Figure 4 shows the desired staggered turn-on sequence of the output voltages.

Some care must be taken when using such an approach. While FETs Q1 and Q2 are in their off state, the output voltages at TP1 and TP2 are unloaded. This could cause the rectified voltages to overshoot by peakdetecting voltage spikes.

Typically, the spikes are due to the transformer’s leakage inductance. This effect can be minimised by adding snubbers across the diodes or by adding preload resistors in parallel with the output capacitors. The drainto- source voltage drops across FETs Q1 and Q2 as the load current increases. Degradation in voltage regulation results with increased loading if care isn’t taken to select a low RDS-ON rated FET.

The use of higher output voltages (>10V) and light load currents (<0.5A) work best with this circuit, and thus are recommended so that the FET voltage drops are negligible. The output-voltage turn-off sequencing depends on the loading placed on the outputs during power down. Any output with a sufficiently large load will collapse the voltage quickly, since there’s only a fixed amount of energy storage available in the output capacitors.

This flyback circuit demonstrates a method for implementing a controlled startup sequence for a SLIC application. However, the same method can be applied to just about any set of power-supply outputs, provided that there is a large enough voltage differential between them. This approach offers a low-cost option and allows for user flexibility in setting the sequencing delays.

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