Electronic Design

Tool Tweaks Algorithms For Low-Power Operation

It's no secret that the performance of digital systems relies heavily on the memory subsystem and the algorithms that control memory accesses. The catch is that these memory accesses consume a great deal of power. Two tools from startup PowerEscape address this problem by tuning algorithms to minimize memory accesses and by optimizing memory architectures for performance.

"Systems are software running on hardware," says Guido Arnout, PowerEscape's president and CEO. "In today's 'everything digital' world, complex algorithms are at the heart of most systems, and these are the things that consume the power."

PowerEscape's products provide source-code-level feedback to tune algorithms for power and performance for a given memory architecture. PowerEscape Analyzer examines ANSI C algorithms and provides reports on memory accesses and the memory subsystem's use of energy, pinpointing code that causes problems.

Conversely, PowerEscape Analyzer+Cache provides feedback to tune the memory architecture itself for a given algorithm. It simulates L1, L2, and L3 caches in many configurations, yielding details of cache efficiency. The tool illustrates the relationship between memory accesses and cache behavior, the amount of energy used by the cache, and which data structures and code segments disrupt it.

The results enable designers to optimize both their source code and memory subsystems, including cache sizes and policies, for lower power. For example, combining the algorithm and architecture tuning can improve an MPEG-2 encoder's dynamic memory energy usage by 2.5 times (see the figure).

CoWare will distribute PowerEscape's tools in an OEM agreement, allowing users to leverage synergies between them and CoWare's system-level design products. A one-year subscription license starts at $10,000.

PowerEscape Inc.
www.powerescape.com

CoWare Inc.
www.coware.com

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