Improving Hierarchical Custom-IC Signal Planning

Improving Hierarchical Custom-IC Signal Planning

The combination of ever-tightening design schedules, increasing design complexity, and shrinking design-feature sizes is driving engineers to automate their custom-IC design flows. Yet upgrading a design flow is a very complex process that involves research, evaluation, and tradeoffs. This tutorial shows custom-IC designers how and where advanced custom signal-planning techniques can be used to potentially automate key design tasks that are now performed using manual methods. These design tasks, which are typically the most interactive and time consuming, are covered in the order of a typical design flow.  

Table Of Contents

  1. Floor Planning
  2. Power Planning
  3. Bus, Long Net, And Data Path Planning
  4. Signal Planning
  5. Signal And Bus Routing
  6. Summary


Floor Planning

The starting point for optimizing hierarchical signal planning and routing involves hierarchical floor planning and optimization. Floor planning for custom designs requires a great deal of flexibility, so support for both top-down and bottom-up approaches is needed to help optimize routing paths, soft-macro (block) floor plans, and soft-macro (block) pin placements.

From a top-down perspective, designers should work with I/O-related signal pins that have fixed positions, plus the overall design’s data flow, to help determine rough positions of hard and soft macros. From a bottom-up perspective, hard-macro locations and pin positions should be used to help estimate and optimize associated soft macro sizes, pin positions, and associated signal routing.

Floor planning is an iterative process that involves many possibilities and permutations. Using an automated tool that supports rapid hierarchical floor-plan generation and prototyping, then, will speed the design process. Although specific IC floor-planning flows often are highly design dependent, a typical hierarchical IC floor-planning process requires these steps:

  • Use fixed top-level pin positions, and refine flexible top-level pin positions later.
  • Analyze top-level dataflow to determine rough-hard and soft-macro positions.
  • Generate soft-macro footprints using placement density estimates plus initial top-level topology information to produce a reasonable “fit” for soft macros.
  • Use an automatic pin placer to determine the first cut of soft-macro pin positions.
  • Trial route the lower-level soft macros to refine soft-macro floor plans, verify routability, and update foot prints and pin positions.
  • Size top-level channels and refine soft-macro pin positions, based on top-level trial routes.
  • Iterate and refine soft-macro sizes and shapes, channel sizes, and macro positions.

A common design practice for projects with flexible design-size targets is to start with initial floor plans that have generously sized routing channels and soft-macro foot prints. This ensures that the routing of early floor plans can be easily closed, which provides early top-level routing-path feedback needed to further refine the hierarchical signal planning.

As the floor plan becomes more mature, routing channels and soft macros with extra space can shrink to help reduce the overall IC size. Key floor-plan factors that will impact hierarchical signal planning include channel width, macro count, macro size, macro location, signal count, signal ordering, and signal/bus topologies such as “L,” “C,” “J,” or “H”-shaped patterns, among other factors.

Power Planning

After determining the basic floor plan and macro sizes, the initial power plan should be added to the design. Aside from hard macros that contain internal power and ground routing, the power plan is normally added in a top-down manner.

The power and ground mesh should always be added before signal and bus routing. Otherwise, signal routing may block the resources needed for power routing. For custom designs with extremely limited metal layers where the power routing is on the same layer as the signal routing, the power structure or mesh should be added before defining the soft-macro pin locations. Otherwise, the structure or mesh pin positions may be blocked by signal pins.

Custom power planning has been traditionally completed by hand drawing and/or coping and pasting metal polygons, vias, and other elements. Recent efforts to automate power planning are based on GUI-based power-planning tools that leverage a higher level of abstraction. This allows designers to interactively create power and ground guides that control the overall topology and connectivity of the power and ground plan. Power guides also include attributes needed to implement the power plan, such as power-supply names, routing layers, routing widths, and related elements.

Aside from power guides, mesh guides can also be created. These guides rely on parameters for the mesh layer(s), mesh width, mesh-stripe counts over macros, and related items. Once these guides are in place, tools can automatically create the actual power- and ground-routing implementation.

Figure 1 shows the position of top-level power-planning guides, where the power and ground guides are placed in the open routing channels between the macros. Example mesh guides are placed over the two soft macros in the center area. The power and ground guides in the GUI provide the recommended routing topology. Plus, they have attributes for routing width, layer, and spacing. If the power plan needs to be updated, the higher-level power guides can be easily modified, and the power implementation can be automatically regenerated.

1. Top-level power-planning guides are placed in the open routing channels between the macros, and the example mesh guides are placed over the two soft macros in the center area.

Figure 2 presents the same view as Figure 1, but with actual power and ground routing based on the mesh guides that figure. The horizontal mesh guides that were placed over the two center macros had attributes to generate six thin power and ground mesh stripes. The guides used in the routing channels were automatically connected together to form the intersecting power topology.

2. The actual power and ground routing, based on the mesh guides of Figure 1, with the same view. The guides were automatically connected together to form the intersecting power topology.

Bus, Long-Net, And Data-Path Planning

The next major step involves adding critical top-level buses. Designers should prioritize and focus on their most critical buses first to give them access to limited routing resources, before moving on to less critical buses.

Buses in custom ICs have traditionally been routed by hand, one tedious bit at a time. If there are major design changes, many buses may need to be ripped up and rerouted by hand. Rather than routing bus signals by hand, a bus-planning tool can be used to quickly input top-level GUI-based bus guides, which provide topology information used to define and optimize the top-level routing paths for corresponding buses.

For example, a single bus guide can provide comprehensive, custom-like routing instructions to route signals for a 128-bit bus. All signal routing for a guided bus follows the same topology and uses the same layer, spacing, and vias so all routes for a particular bus will have similar timing by design.  

Inputs for bus guidance include the physical topology (added interactively), signal ordering, optional shielding, optional signal interleaving with other buses, metal-layer selection, via selection, and via-topology selection for forward or backward via sets. Various generic controls can be provided by using an attribute editor, which can define buses by combining signals together, set signal-routing widths and spacing, and select X, Y routing layers.

Figure 3 shows two examples of bus-routing guides between two neighboring dark-green macros. The dark-blue horizontal bus guides are overlapping, causing these routed bus signals to be interleaved. If the horizontal guides were separated, the bus signal routing would also remain separated. The light-blue trapezoids represent the vertical routing connections from the macro pins out to the horizontal dark blue horizontal bus guides.

3. In these examples of bus-routing guides between two neighboring dark-green macros, the dark-blue horizontal bus guides overlap, and the light-blue trapezoids represent the vertical routing connections from the macro pins out to the horizontal dark blue horizontal bus guides (a). Vertical routing connections and horizontal bus guides are visible in an expanded view (b).

Bus-signal interleaving can be used to minimize cross-talk effects by alternating the routing for bits of two buses that are active at different times. Also note, bus bits can be twisted or reordered to choose adjacent-bus signals that potentially have lower cross-talk effects. When using automated bus-guide-based flows, buses that don’t require routing guides can be routed later on, just as ordinary signals would be routed.

Figure 4 shows bus routing based on the two bus-routing guides of Figure 3. The routing of the two horizontal buses is interleaved because their horizontal guides are overlapping. In this case, the two buses have different bit widths, and interleaving specified by the settings puts the eight bits closer to the figure’s lower edge. The bus signal via orientation can be specified as forward or backward, and it’s usually chosen to minimize signal crossing.

4. With the bus routing based on the two bus-routing guides in Figure 3, the routing of the two horizontal buses is interleaved. Here, the two buses have different bit widths.

Once the bus guides are in place, the buses can be routed. Afterwards, a topology-based repeater planner can be used to specify the repeater-cell model and locations for bus-repeater insertion. (Repeaters are typically added to speed up signal propagation and reduce cross-talk effects.) The next step is to automatically place and connect the repeaters to the bus routing. Propagation delays for signals on the same bus will be very close, since their routing and buffering will be similar.

Signal Planning

Signal planning is often a time-consuming process that can impact design schedules as well as area requirements for hierarchical custom design. Signal planning benefits from the use of comprehensive signal-planning tools that can support two approaches: strictly biased routing and multiple-bias routing, which uses a jumper layer.

Strictly biased mode limits signal routing to user-specified X- and Y-routing layers without exceptions. Many routing tools provide this capability. Multiple-bias routing mode is an advanced capability that supports signal routing on the same metal layer for both X and Y directions. Meanwhile, a jumper layer can be defined and used to cross other signals that are blocked by existing X, Y multi-biased routing.

For example, signals could use multi-biased metal-3 routing for both X and Y directions, while using metal 2 as a jumper layer. In this case, the metal-2 jumper layer is used when metal-3 routes in the perpendicular direction block multi-biased metal-3 signal routing. These biased-routing capabilities enable designers to employ multiple, complex space-saving routing topologies such as “L,” “C,” “J,” and “H.”  

Additionally, signal routing can be stacked into complex patterns for processes with deeper metal stacks. Processes with limited metal stacks that include a high-resistance routing layer could use that routing layer as a jumper layer, increasing available routing resources without seriously degrading timing.

Different biased signal-planning attributes can be applied to specified sets of signals, so the routing can be customized as needed within different parts of the design. All routable signals have unique user-defined attributes and constraints such as metal width, metal spacing, routing layer, net shielding, via selection and usage, path length, path delay, path capacitance, and path resistance.

Signal And Bus Routing

Once the floor plan, power plan, bus plan, and signal planning are in place, then various routing capabilities are often needed to implement the hierarchical design. For example, a global router can be used for rapid congestion-analysis feedback to help optimize the floor plan’s macro placement and channel sizes, removing routing bottlenecks before employing a Manhattan-shape-based router.

An automatic shape-based router that supports Manhattan routing and angled routing can be used to avoid creating unnecessary jogs, minimize via counts, and minimize wire length. Design nets are sorted and ordered to further minimize wire crossing and via usage, which supports more efficient utilization of limited routing resources while boosting production yields.

Since the underlying router is shape based, it can view the entire routing database at one time. Shape-based routers do not use routing “bins.” As a result, signals aren’t shunted unnecessarily through distant routing bins to address routing-congestion hot spots.

Due to this unique approach, signal routing takes straight and direct routes rather than longer “scenic” routes that are typical of bin-based routers. Critical signals and buses can also be selected and routed before less critical signals and buses so they have earlier access to limited routing resources.

A bus planner and router can be used to support guide-based bus routing and repeater insertion. The routed bus signals follow matching routing topologies and use the same routing widths and via sizes.

A spine-and-stitch routing capability can be used to route channels as well as designs that have long, thin aspect ratios. The spine-and-stitch router can optimize the use of very limited routing resources in one direction. The spine route typically connects many loads, but only uses one track (the spine) in the direction that has limited routing resources, to the perpendicular routes from the spine route (called stitch routes). These stitch routes are routed orthogonally from the spine to destination pins.

Figure 5 shows an example net, highlighted in white, routed using a spine and stitch router. This net connects to 68 pins, but uses only one long, low-resistance horizontal-routing track, called the spine route. The 25 vertical-stitch routes are made with perpendicular connections to the spine route. The short horizontal-routing stubs (or pins) at the far ends of the stitch route use a high-resistance routing layer.

5. In white, the example net routed using a spine and stitch router uses only one horizontal spine route to connect to 68 pins and has 25 vertical stitch routes running perpendicular to the spine route.

Manual routing capabilities have historically been very important to the custom-design community. An intuitive GUI should provide a wide variety of interactive routing features, and these features include shortcut keys that can set attributes that specify the metal width, metal spacing, via topologies, and related characteristics.

Additional capabilities can be used to automatically move and spread selected signals to free up local routing space. Furthermore, an online design-rule checking (DRC) capability can be automatically run to check manual routing edits and provide the instant feedback needed to maintain design-rule correctness. Routing can also be completed by using semi-automatic routing methods that involve a mix of manual routing plus automatic routing.


This tutorial has presented a diverse set of hierarchical signal routing and features and capabilities. By definition, custom designs have unique requirements and attributes. It follows that “one size fits all” digital-design solutions probably won’t have the flexibility needed to support the wide range of custom-design automation requirements.

In general, custom-design tools should use a design database that supports visibility throughout the design hierarchy so floor planning, bus planning, signal planning, and pin placement can be efficiently optimized, using both bottom-up and top-down approaches. Once the hierarchical signal-planning effort is complete, a wide variety of routing capabilities can be employed to route hierarchical signals, while using topology guidance along with routing attributes such as routing layer, route width, via size, and via orientation.

This approach optimizes the hierarchical routing connections while minimizing routing lengths so scarce routing resources are used more efficiently. Designers will benefit from using signal planning and routing tools that provide these capabilities to hierarchically plan and route signals and buses in complex custom ICs:

  • Spine-and-stitch router for extreme aspect-ratio routing
  • Shape-based router to provide straight-direct connections
  • Multi-topology router for compact bus and signal connections
  • Multiple-bias routing for compact X, Y routing on one layer
  • Seamless integration of soft-macro placement and pin placement
  • Fast hierarchical prototyping
  • Net sorting and ordering for routing to minimize routing and crossovers
  • Constraint-driven routing for fine-grained control        
  • Post-route jog and via optimization to improve performance and yield
  • Automated DRC and density- and antenna-checking and fixing
  • Automated ECO implementation
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