SURVEY OF HIGH-PERFORMANCE CPU ARCHITECTURES
Processor Size Feature Advantages
AMD Opteron 64 bits
  • Advanced HyperTransport
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  • Peripheral interconnect
  • ccNUMA memory architecture
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    Arm ARM10 32 bits
  • Return-stack caching
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  • Recognizes indirect branches using register 14 to eliminate pipeline flush on subroutine return
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    Broadcom BCM1400 64 bits
  • Quad 64-bit processing cores
  • Triple Advanced HyperTransport/SPI-4 links
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  • Quad multiprocessing
  • Extensible ccNUMA architecture, high-speed serial packet support
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    Cyan eCog 16 bits
  • Lockable cache
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  • Programmatic control over caching, allowing small routines to be maintained in cache
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    Cygnal C8051F120 8 bits
  • Prefetch buffer with 256-byte instruction cache
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  • Single-cycle instruction access from flash memory
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    IBM PowerPC 64 bits
  • Copper and silicon-on-insulator technology
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  • Low power, small die size, improved performance
    		•
    Intel Itanium 64 bits
  • EPIC Explicitly Parallel Instruction Computing
  • Level 3 cache
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  • Parallel instruction processing
  • Better support for data-intensive applications, such as database servers
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    Intel Xeon 32 bits
  • Hyper-threading
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  • Dual processing power on one chip
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    Intel Pentium 4 32 bits
  • Hyper-pipelining
  • Execution trace cache
  • Rapid execution engines
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  • Twice the length of prior Pentium pipelines, faster instruction and load/store execution
  • Stores decoded micro ops, eliminating decode delays for cached instructions
  • 1/2-cycle instruction execution times
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    MIPS MIPS64 64 bits
  • SIMD floating-point instructions
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  • Accelerates processing of large data streams, eliminates the need for a separate DSP
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    Motorola HCS12 16 bits
  • Three-word instruction queue
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  • Single-cycle instruction access from flash memory even during loops
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    Motorola PowerPC 32 bits
  • RapidIO interconnect
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  • High-speed peripheral interface
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    SuperH SH-5 64 bits
  • Four-way integer SIMD
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  • Accelerated multimedia processing
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    TI OMAP 32 bits
  • CPU/DSP dual processor
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  • Each processor handles appropriate algorithm
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    Ubicom IP2202 8 bits
  • Memory-to-memory architecture
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  • Efficient packet processing
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