Achronix Semiconductor's latest Speedster FPGA is packed full of hard core interfaces such as PCI Express. It is based on Intel's 3D 22nm FinFET transistors and targets high performance applications (see Moore's Law Continues With 22nm 3D Transistors). The Speedster 22i HD (High Density) version utilizes a conventional interconnect. The Speedster 22i HP (High Performance) version will utilize the PicoPIPE interconnect of its current chips (see Speedy 22nm FPGA Packs PicoPIPEs). The PicoPIPE architcture provides a clock gate asynchronous FIFO interconnect that can further increase FPGA clocking speeds while lowering power requirements (see 1.5-GHz FPGA Takes Clock Gating To The Max).
The use of hard core interfaces saves significant space (Fig. 1) as well as reducing power requirements. It can cut power needs in half compared to a soft IP-based peripheral solution. Likewise, the FPGA design, layout, and place-and-route becomes easier and faster when these peripherals do not have to be included in the mix.
Figure 1. A conventional FPGA (left) using soft peripherals leaves significantly less space available for applications compared to the Speedster HD (right) that has hard peripheral interfaces space around the chip.
This leaves more space for logic. The top end HD1500 has over a million 4-input LUTs (lookup table) and 864 28- by 28-bit MACs (multiply accumulate) blocks. It also has 138,240 Kbits for block RAM. In addition to digital I/O the chip has 64 12.75 Gbit/s SERDES and 16 28 Gbit/s SERDES. Each SERDES is independently clocked and has fine grain pulse width control.
The Speedster HD is no slouch when it comes to speed though and part of its efficiency comes from its hard core peripherals. These include up to six DDR 3 controllers supporting up to 72-bit banks, two PCI Express Gen 3 x8 interfaces with DMA support, two bansk with 10/40/100G Ethernet MACs and two banks of 100G Interlaken interfaces. The latter suports twenty 6.5G links, twelve 10G links or ten 12G links. The Ethernet support maxes out with 48 10G, 12 40G and 4 100G interfaces (Fig. 2). The HD1500 has a total bandwidth of 4.5 Tbits/s.
Figure 2. The Speedster HD comes in a range of configurations.
The packaging is also compact with 1,401 I/O pins in a 52.5 by 52.5 by 1 mm package or a low profile, 45 by 45 by 0.82mm chip. Another 45 by 45mm package reduces cost but cuts the numbe of I/O pins downs to 881. The smallest 25mm by 25mm package houses an HD210 with 268 I/O pins, no 28 Gbit/s SERDES and a pair of DDR3 controllers.
The Speedster HD is going to have a major impact in communications-related FPGA applications. It is ideal for packet processing providing a bridge between Interlaken and Ethernet interfaces. It is also going to impact ASSP and even ASIC designs because these new Speedsters can get closer in terms of performance and power requirements while maintaining flexibility and reduced design time. A typical large scale FPGA often requires 4 months of timing closure design time compared with half that of the Speedster 22i because of its hard core IP.
The Speedster line is supported by Achronix's ACE (Achronix CAD Environment) that handles place-and-route, timing analysis, and bit stream generation. It also provides the in-system debug interface. The Eclipse-based platform runs on Windows and Linux.