To accompany the release of its Stratix II FPGA family, Altera has updated its Quartus II design software with version 4.0 to handle the new devices' advanced architecture and expanded gate capacities.
The Stratix II FPGAs sport an adaptable architecture based on what Altera calls an "adaptive logic module," or ALM, which allows logic to be shared among adjacent logic functions (see "Adaptive Logic Molds Faster, More Efficient FPGAs," p. 48).
The new Quartus II release can target both FPGAs and structured ASICs. Altera's LogicLock methodology lends itself to a true block-based flow that facilitates IP reuse and team-based design.
The SOPC Builder tool within the Quartus II suite further supports IP-based design. SOPC Builder includes complete, automated system definition and implementation capabilities without the need for lower-level HDL or schematics. The tool leverages an extensive set of IP from Altera and its IP partners.
A broad array of timing-closure technologies are available within Quartus II. Integrated physical synthesis applies knowledge of the silicon itself to the compilation process. The Design Space Explorer tool gives users a control panel from which to explore a full range of optimization options. The latter, coupled with incremental compilation, provides exceptional flexibility for tweaking designs.
Place-and-route enhancements deliver an average maximum frequency improvement of 50% and 18% faster compile times when targeting Stratix II devices.
Annual subscription pricing for version 4.0 of the Quartus II design software is $2000 for a node-locked PC license.