The third-generation ProASIC family of flash-based FPGAs, the ProASIC3 and 3E series from Actel, combines logic densities ranging from 30k to 1M system gates (ProASIC3) and 600k to 3 million system gates (ProASIC3E). Per-chip costs start at $1.50 each in lots of 250,000 units. In all, there are seven family members that cost less than $10 apiece with capacities of up to 1 million system gates.
The flash-based devices can be reconfigured in the field. They have no "boot" time, and they don't require a separate configuration memory. As a result, they deliver a lower system cost and component count than systems based on SRAM-based FPGAs. In addition to the logic fabric, the FPGAs also include up to 144 kbits of true dual-port RAM (up to 504 kbits on the "E" series).
Every chip in the family includes a wide range of I/O options. The A3P250 and larger versions include 700-Mbit/s double-data-rate and low-voltage, differential-signaling-capable I/O cells. Multiple clock-conditioning circuits and phase-locked loops are included on all chips except for the A3P030.
A 64-bit PCI interface can be implemented on all versions large enough to support the macro. Up to 350-MHz system-level performance is achievable. In addition to the flash memory that holds the logic configuration, Actel designers added 1 kbit of user-programmable flash data storage that can hold whatever data is defined by the user.
To keep the configuration data secure, there's an on-chip 128-bit Advanced Encryp-tion Standard decryption engine that can decrypt an encrypted configuration data stream. The company also includes its own FlashLock security scheme to prevent configuration data from being read out.
Actel Corp.www.actel.com