Electronic Design

Digital ICs> Cost-Saving 90-nm Processes A Boon To FPGA Markets

One bright spot in an otherwise dreary ASIC market landscape is the progress made by the FPGA market in terms of improved performance and cost. Toward the middle of 2004, the first FPGAs produced using 90-nm process technology will enter the market in volume. It's very likely that the upper end of such a family will include at least one chip that packs 1 billion transistors, offering greater performance than the market has ever seen from an FPGA. Furthermore, it's also highly probable that these parts will be manufactured using 300-mm wafers.

Paradoxically, as the value proposition for other types of ASICs manufactured using 90 nm becomes more difficult to validate, it becomes easier for FPGAs. The reason is simple. FPGAs, due to their "standard product" natures, are ensured reasonably large end markets. On the other hand, ASICs by their very nature don't have the same certainty across all possible applications. Large end markets drive reasonably large unit volumes and thus lower unit costs. The requirement for increased functionality and performance are also constant drivers of this market. It's easier for FPGA vendors to make the case for using cutting-edge process technology sooner in the lifecycle than it is for other, alternative types of ASIC products. The net result will be higher-performing parts at lower-cost points than the industry has seen to date.

The second impact from moving to 90-nm technology is an opening up of new markets and applications as chip costs dwindle. FPGA vendors have been willing to embrace new opportunities and incorporate new functionality as the performance of their parts increases over time. The lower-cost points for a given performance range potentially enable FPGA vendors to remain in the application longer into the production ramp-up of the system and may bring increased revenues for the market.

A third area of impact on the FGPA market will be the incorporation of mid- to high-level analog functions on FPGAs. This could take the form of high-performance digital-to-analog converters or analog-to-digital converters. It's very likely that most of the FPGA vendors will offer some type of analog functionality beyond that of phase-locked loops or SERDES channels by the end of 2004 or the beginning of 2005.

A fourth area of impact will be the continued use of FPGAs to test and validate different blocks of semiconductor intellectual property (IP). The IP industry is on the rise as vendors offer better performing products to users, which leads to the solving of problems that have hampered the market.

However, one area of continuing concern is the issue of interoperability between different semiconductor IP blocks from different IP vendors used in the same design. This consumes as much as 70% of the time designers spend in proving out their designs. FPGA vendors offer a powerful alternative to testing the IP blocks. Because the architecture of a FPGA is deterministic—the silicon is known, proven, and tested before it enters the market (as compared to a standard-cell or system-on-a-chip approach where every design is unique)—the testing and use of IP blocks on FPGAs is a much simpler task. It allows designers to finish their design more quickly and at a much lower cost. In today's market, lower costs and shorter design-cycle times are powerful inducements for using a product.

Semico Research Corp. believes the FPGA market is now recovering and will continue to grow, reaching $2.6 billion by the end of 2005, up from just over $2.0 billion in 2003. The entire programmable-logic market also shares in this growth as it increases from $2.6 billion in 2003 to $3.4 billion by 2005.

TAGS: Digital ICs
Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish