Flash FPGAs Incorporate Differential Power Analysis Countermeasures

Flash FPGAs Incorporate Differential Power Analysis Countermeasures

The IGLOO2 extends Microsemi's flash-based FPGAs reach and it adds new features like differential power analysis (DPA) countermeasure technology to prevent counterfeiting and hardware attacks. DPA support was licensed from Cryptography Research, a division of Rambus. DPA support applies to the chip as a whole, not just a memory or cryptography/security subsystem. This means a powered chip will always be radiating power in a random fashion but the actual overhead tends to be low.

The 65-nm IGLOO2 FPGA (Fig. 1) uses an instant-on, flash-based FPGA fabric. This is the same kind of technology used in Microsemi's other FPGA platforms like the compact IGLOO nano (see FPGA Costs Half A Buck) and the SmartFusion (see FPGA Combines Hard-Core Cortex-M3 And Analog Peripherals) line that includes a hard core Cortex-M3 processor.

Figure 1. The IGLOO2 FPGA uses an instant-on, flash-based FPGA fabric. It includes a range of hard logic blocks including memory interfaces and 5G SERDES.

The DPA support is designed to prevent reverse engineering and other attacks that try to use the power emissions from the chip. The chip includes a hardware random number generator (RNG). Other security features designed for the developer including AES encrypt/decrypt support as well as support for other encryption standards.

The FPGA design addresses single event upset (SEU) noise immunity. SEU becomes more important as design geometries shrink. SEU support is incorporated into the on-chip flash and RAM storage as well as the FPGA fabric flash storage.

The flash-based storage allows Microsemi to deliver its Flash*Freeze mode. This mode can lock the outputs while powering down the FPGA to reduce power requirements. The flash-based FPGA fabric means that start up times are minimal allowing the FPGA to operate like many microcontrollers that sleep most of the time. Events can be programmed to allow the FPGA to exits this mode.

The IGLOO2 targets cost optimized, high performance applications. The family supports up to 150 K logic elements (LE) and 240 DSP math blocks. It includes a number of hard core interfaces to simplify design and improve efficiency and power utilization.

The chips have up to sixteen 5 Gbit/s SERDES that can be used for standard interfaces like PCI Express and Ethernet. The family supports up to four individual PCI Express endpoints.

The memory subsystem incorporates up to 512 Kbytes of eNVM memory, something typically found off-chip on other FPGAs. On-chip RAM maxes out at 5 Mbits. Off-chip memory support includes up to a pair of 36-bit DDR memory controllers that can work in conjunction with a pair of DMA controllers. The memory subsystems is linked to the FPGA fabric using a pair of fabric interface controllers (FIC).

Microsemi simplifies the power management of the system by requiring only two supply voltages, 1.2V and 3.3V for I/O. Most FPGAs require 3 voltages. Chips are available for military and avionic use.

The DPA and SEU support make the IGLOO2 a security processing environment. Even the program for the FPGA's fabric can be checked before it is loaded.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish