As FPGAs grow larger, incorporate more on-chip resources, and become more like ASICs in many ways, FPGA design flows must evolve with them. The latest iteration of the PlanAhead design analyzer follows on the heels of a revision of Xilinx's ISE design suite to forge a flow that brings performance and design advantages to users of the company's silicon.
Version 8.1 of PlanAhead streamlines the step between synthesis and place and route to give designers more control and insight into how their designs are implemented. According to Xilinx, PlanAhead 8.1 can buy users of its design flow up to 30% better performance on average compared with other FPGA implementation tools. For complex, multiclock designs, that performance gain can be as much as 56%. This translates into a two-speed-grade advantage.
Further, PlanAhead is the key to exploiting the partial-reconfigurability features built into the latest revision of ISE. Now, predefined portions of an FPGA can be reconfigured while the remainder of the design continues running. The tool simplifies the creation of dynamic modules and lets users create multiple floorplans for a given design implementation.
Also new in PlanAhead 8.1 is the ExploreAhead feature, which enables users to look into alternative place-and-route options for their designs. Multiple floorplans can be generated from a single netlist.
PlanAhead 8.1 is available on all major operating systems as an option to the ISE design suite. Single-user licenses cost $5995.