Electronic Design

FPGA Physical Synthesis Flow Takes Aggressive Approach To Timing

Today's 90-nm FPGAs are a good-news/bad-news proposition. The good news is that such devices carry abundant resources. The bad news is that they can pose difficulties in timing closure, especially with tools whose timing estimates don't correlate well with back-end results. Synplicity's Synplify Premier comprises a pushbutton physical-synthesis flow that purports to remedy this problem.

At the heart of Synplify Premier, Synplicity's graph-based physical-synthesis technology takes advantage of the tool's ability to perform placement and routing simultaneously with all iterations done within a given run. In the graph-based approach, the tool creates a detailed routing-resource database of pre-existing wires, switches, and placement sites within the device. Instead of distance measurements alone, the database permits wire delays and actual availability of resources to drive placement and routing. Placement is congestion-aware for high-fanout nets.

The tool's output is a design that's fully placed down to the lookup-table level, with pins on logic blocks assigned. Because the back-end tools have the benefit of accurate timing data, optimizations can be extremely aggressive, even to the point of optimizing away levels of logic. Synplicity's tests on Virtex-4 designs show that about 90% of designs done with Synplify Premier are within 10% of timing correlation with final placed-and-routed results.

The tool also brings advantages for designers prototyping ASICs in FPGAs. It performs gated-clock conversion and handles generated clocks as well as Synopsys DesignWare IP. Teaming the Synplify Premier with Synplicity's Certify RTL prototyping tool lets designers create multiple-FPGA prototypes.

Available now, Synplify Premier starts at $34,000.

Synplicity
www.synplicity.com

TAGS: Digital ICs
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