Electronic Design

FPGA Synthesis Adroitly Handles Late Incremental Design Changes

FPGA synthesis comes with pitfalls that are becoming more of a liability as the devices themselves grow in complexity. Timing closure can take multiple synthesis iterations. Also, design iterations are getting longer. Last-minute design changes mean a full place-and-route run, requiring hours for a large FPGA. And, it's difficult to control and analyze how logic is mapped to device-specific blocks.

Mentor Graphics' Precision RTL Plus tool takes these issues head-on. It offers an average Fmax improvement of 10% over the earlier Precision RTL tool with typical gains of 5% to 40%. Supporting 19 FPGA families, it covers a range of devices from multiple vendors.

Precision RTL Plus performs a global placement with awareness of the FPGA's routing resources as well as of basic design-rule checking. The tool determines critical paths before performing synthesis to create an optimized netlist before full placement and routing.

Two incremental synthesis flows address lengthy iterations. One is fully automatic and requires no partitioning. The other is partitionbased for a divide-and-conquer approach. The automated flow couples with Xilinx's SmartGuide technology for a fully automatic incremental synthesis and place-and-route flow. Prices start at $27,100.

Mentor Graphics
www.mentor.com

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