Electronic Design

FPGAs Implement SFI-5 For Faster Throughput

Altera’s implementation of the SERDES (serializer/deserializer) Framer Interface Level 5 (SFI-5) specification really ramps up the speed. The company’s Stratix II GX FPGAs with embedded transceivers support the spec’s 40- to 50-Gbit/s aggregate data throughput requirement (see the figure). SPI-5 is a chip-to-chip standard for interoperability between the forward error correction processor, the framer, and compliant optical transponder devices.

The company has hardware-tested the Stratix II GX devices to verify compliance to the SFI-5 standard. These FPGAs support the data throughput rate with up to 20 high-speed transceiver channels that can manage between 600 Mbits/s and 6.375 Gbits/s. Thus, they can achieve 50 Gbits/s with several channels to spare.

The Optical Internetworking Forum (OIF) developed the SFI-5 specification to provide a communication channel between network processing devices and optical transponders for high bandwidths. It supports the OC-768, SMT256, and OTN OUT-3 network transport formats.

“The SFI-5 standard, as implemented in our Stratix II GX FPGAs, is being adopted rapidly by high-performance optical communications systems,” said David Greenfield, senior director of product marketing, high-end products, at Altera. “For designers developing next-generation wireline communications applications, our Stratix II GX FPGAs easily exceed the demanding SFI-5 signal integrity and skew requirements with ample margin.”

Production-qualified Stratix II GX FPGAs, with support for the SFI-5 protocol, are available now.

Altera

www.altera.com/sfi5

TAGS: Digital ICs
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