Electronic Design

FPGAs Ride Tools Into ASIC Territory

As their on-chip resources and gate count grow, more ASIC-like implementation flows push FPGAs into unlikely applications.

When pondering your next-generation system design, you may ask yourself whether the spiraling mask costs have priced you out of the ASIC game. You'll perform the requisite analyses of performance requirements (high) versus cost (much higher) and begin wondering whether another implementation path might serve the end product in a more costeffective fashion. And you'll consider the notion of using FPGAs, at least for prototyping if not for production. FPGAs? Can they have the horsepower to make that nextgeneration design sing? With major FPGA vendors now at the 90-nm process node, it's quite likely they do.

Endowed with a wealth of on-chip resources, today's highend FPGAs can take on circuits that looked ASIC-bound. And FPGAs will soon hit the 65-nm node, and with that, they'll reach new heights in terms of density, performance, and their ability to move signals onto and off of the chip (see the table).

But it's not the silicon alone that forms these FPGAs. Tool flows for FPGAs, both from the silicon vendors and from third-party EDA vendors, continue to evolve to support the chips' burgeoning capabilities.

USAGE MODES
Generally, there are two broad categories of tools for FPGA implementation. One category comprises the tools provided by the FPGA vendors at low cost, or even gratis. In most cases, these tools are dedicated to the vendors' own devices. A corollary is the tools provided by FPGA vendors in OEM arrangements with EDA vendors; such tools are limited to a given FPGA vendor's silicon. The tools can fit the bill for designers who have settled on a given FPGA vendor.

The second category involves tools from EDA vendors that are FPGA vendor-independent. Designers often will want to benchmark their circuit on FPGAs from various makers. Vendor-independent implementation flows make this an easier process than having to switch from tool set to tool set.

Further, FPGA users typically fit into two major camps. One uses them to prototype an ASIC or other full-custom IC. For these users, the FPGA is little more than a verification vehicle on which they prototype parts, or all, of their ASIC design. The idea here is to mitigate risk before entering into the costly process of committing to custom silicon.

"About 60% of the systems customers we deal with are using FPGAs for prototyping before going to standard-cell, large-volume production," says Sanjay Bali, product director for front-end solutions at Magma Design Automation.

"If you look into using FPGAs for prototyping, the requirements for tool use are very different from those who use FPGAs for production silicon," says Juergen Jaeger, director of marketing for Mentor Graphics' DCS Division.

When it comes to prototyping, these users may not necessarily be experts in FPGA tool flows. But they're trying to map their ASIC designs into FPGAs in the easiest possible manner. They need their FPGA tools to handle ASIC-style designs, including a mixture of languages and levels of abstraction.

Also critical when prototyping with FPGAs is the tools' ability to handle design constraints. They must also be able to take in the Synopsys .sdc constraint file format.

"Things like the quality of results (QoR), which, in the FPGA world, really means the maximum frequency (FMAX) at which the design can run as well as gate utilization, are not so important in the ASIC prototyping world," says Mentor's Jaeger. "You're not running as fast as the ASIC would, but you're still running a lot faster than the simulation."

What is critical, though, is preservation of functionality. Because prototypers use the FPGA for verification, they also require fast design iteration times. This means that their tools should support an incremental design methodology so that small changes can be implemented quickly without having to recompile the entire design.

The second major mode of usage for FPGAs is when the FPGAs themselves are the final implementation vehicle for the circuit. In this case, FPGAs are used in production and not just for prototyping. Thus, QoR is obviously a much more important issue, both in terms of speed and gate utilization. The designer also needs deep insight into the devices' onboard resources and how they're used most effectively.

TOP-DOWN TACTICS
Many ASIC-oriented design approaches have filtered into the FPGA world. One involves the notion of top-down design starting from a high-level design description. More designers are gaining confidence in the concept of starting design at the algorithmic level and using C-based languages.

Celoxica is one vendor whose tools accept C-language design entry. This approach to design affords a number of advantages. For one, system simulation is much faster. For another, working in a C-language environment facilitates hardware/software codevelopment and coverification.

Tools like Celoxica's Agility Compiler, a C synthesis tool, are especially useful for hardware developers who have adopted use of transaction-level models. The Agility Compiler enables raising the abstraction level above that afforded by SystemC, which, according to Jeff Jussel, Celoxica's vice president of marketing, is "very restrictive as a synthesizable subset." As a result, the Agility Compiler retains standard C datatypes and also allows for use of all C++ class libraries.

Mentor Graphics has also ventured into the C-level world of FPGA design with its Catapult C synthesis tool, which takes in a C functional description and produces a Verilog or VHDL description. Moreover, that HDL code is tailored for the designer's specified FPGA.

With the Agility Compiler and Catapult C, exploration of numerous microarchitectures is possible. Because the system is described in a highly abstract manner in C code, the synthesis tools can be instructed to implement it in a more parallel structure, or, if desired, a more sequential structure. Designers can either try to gain the fastest possible implementation using pipelining or to minimize area. Iterations are generated very quickly and are accompanied by spreadsheets and graphs for comparison of microarchitecture variants. In contrast, attempting to sort through these iterations manually could take multiple weeks for each microarchitecture.

Designers have had good success with FPGA design starting at a high level of abstraction. "Adoption of a high-level design methodology for FPGAs is driven by applications with complex algorithms that change rapidly," says Jussel. "You can't afford to fix these functions in static hardware." Such applications also often require hardware acceleration and can make use of the massive parallelization provided by FPGAs (see "From Algorithms To HDTVs," Drill Deeper 13475, at www.electronicdesign.com).

INCREMENTAL CHANGES
Incorporating high-level design methodologies into the FPGA world is one way in which FPGA users are seeing a more ASIC-like flow. Another technique is incremental-design technology. Tools that allow incremental design will recompile only those portions of the design that changed since the last compilation. The rest of the design remains unchanged.

FPGA users are incorporating jazzy interfaces such as highspeed SERDES as well as DDR. "Being able to modularize and fix certain blocks, and thereby creating an incremental change capability, is critical to users," says Tim Schnettler, director of software marketing at Lattice Semiconductor.

Incremental design capabilities enable teams to split up designs and let the experts work on the pieces that they know best. Further, they can allow reductions in design iterations of up to 70%, which was Altera's goal for the incremental compile capability in its Quartus II design suite.

According to Chris Balough, director of software and Nios marketing at Altera, today's largest FPGA designs can take from one hour to over four hours to perform a full compilation. "This means that you can only perform two iterations a day for significant design changes. We found this to be a major bottleneck in the design process," Balough says.

The incremental compile feature in Altera's Quartus II suite lets designers go from one or two iterations a day to as many as four or five (Fig. 1). This can be extremely useful during the verification stage.

Xilinx's tool set includes the PlanAhead tool, acquired along with Hier Design some time ago. PlanAhead, which is now in version 8.1i, enables Xilinx to provide a complete partial reconfiguration flow for its FPGAs. "With PlanAhead, users can define partitions for static and dynamic blocks," says Balaji Thirumalai, senior marketing manager for Xilinx's logic design tools. PlanAhead automates the task of floorplanning those static and dynamic partitions.

DSP TAKING PRECEDENCE
"A huge trend in emerging FPGA applications has been in the DSP area," says John Gallagher, director of outbound marketing at Synplicity. Gallagher cites applications in military/aerospace systems, radar installations, satellites, and terrestrial radio.

The massive parallelization that's possible with FPGAs lends itself well to DSP applications, as well as other signal-processing scenarios. For instance, Xilinx has worked closely with the MathWorks to provide a plug-in for design with the latter's Simulink environment.

Xilinx's System Generator for DSP employs Xilinx's DSP function library and plugs those functional elements into either HDL or a bitstream for use in programming the functions into an FPGA. Xilinx's Accel DSP tool also figures into this flow. Accel DSP translates Matlab algorithms into HDL. Xilinx has been investigating ways to import the HDL that's generated by Accel DSP into System Generator for DSP.

Xilinx also teamed up with Synplicity to improve DSP resource utilization in Xilinx's Virtex FPGAs. Synplicity's Synplify DSP synthesis tool automates DSP implementation. It also provides for fast design-space exploration, thanks to its ties to the MathWorks' Simulink environment (Fig. 2).

Some interesting system implementations have been put in place using FPGAs for signal-processing applications. One, designed by the Center for Microelectronics at Aargau, Switzerland, involved a 32,768-point fast-Fourier transform (FFT) that pushes the limits of what can be implemented in a Virtex-2 Pro FPGA (see "An FPGA-Based Spectrometer For Solar Observation," Drill Deeper 13476).

DESIGN ANALYSIS
An ASIC-like flow for FPGA design demands ASIC-like design analysis, and both FPGA vendors and EDA vendors have stepped up to the plate in this respect.

On the power-analysis and optimization side, QuickLogic's QuickWorks suite of implementation tools includes what the company calls its PowerPlacer capability. Rather than perform place-and-route operations with only timing in mind, the PowerPlacer capability accounts for both timing and power.

QuickWorks also incorporates a power calculator, which presents worst-case power-consumption analysis and performs what-if analysis. On top of that, a power simulator takes in a netlist and shows which blocks in a design consume the most power. The results of the simulation can point the designer to problem areas in the circuit.

Actel's Libero integrated design environment, now in version 7.2, offers advanced power and timing analysis capabilities for users of its Fusion, ProASIC3, and RTAX-S logic families. Actel's SmartTime feature offers static timing-analysis capabilities based on standards such as the Synopsys design constraints, as well as visual constraint dialogues that help ease the transition from ASICs to mixed-signal FPGAs. Clock-source latency analysis, which allows the definition of a clock constraint for jitter, helps designers to analyze FPGA timing in the context of its surrounding environment.

Actel's SmartPower analysis tool was upgraded to generate power-consumption data for nets, gates, I/Os, RAM, FIFOs, and clocks. Or, it can generate data block-by-block by component type.

TAKING A SYSTEMIC VIEW
When contemplating any system integration, whether with ASICs or FPGAs, it's important to remember that the devices aren't designed and implemented and then thrown into a drawer. They must be developed with software in mind. Further, the designer must think in terms of the FPGA existing in residence on a pc board.

Altium's Designer suite of tools and associated development boards provide a single executable environment that handles FPGA design, board design, and full software development capabilities. The environment is fully interactive in that hardware and software are developed concurrently and with each domain having full awareness of the other.

"In our view of FPGA technology, we see it as a bridge between the hardware and software realms," says Rob Irwin, Altium's product marketing manager. "Our approach is to use the FPGA technology to unify the development of the hardware and software pieces of the puzzle."

On the chip-to-board side, the same kind of interactivity allows board design to be accomplished with full knowledge of the associated FPGA's pinout. If either the FPGA or board layout is changed, the other is changed to reflect it.

In a similar vein, Mentor Graphics' I/O Designer is intendedto close the gap between the FPGA and its interface to the pc board. I/O Designer aids the board-layout software in determining whether pins can be swapped. It also creates the pc-board symbols for the FPGA, which can be a time-consuming step.

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