The XLArray family of gate arrays is said to accelerate the process of converting high-density, high-performance, deep-submicron FPGAs, such as Altera’s APEX and Xilinx’s Virtex products, into cost-effective ASIC designs. With the new gate arrays, the firm expects to take customers’ prototypes from layout to silicon in as little as three weeks, contributing to significantly reduced time to market for end products.In filling the gap between high-end, costly FPGAs and high-volume standard cell parts, the XLArray gate arrays also are said to reduce the cost of transitioning to volume production. The firm claims a 2x to 4x reduction compared with FPGA implementations. The devices meet the needs of users in markets such as data communications, telecommunications, consumer electronics, and industrial and military applications.The XLArray is a 0.35-µm gate array family with an architecture designed specifically for conversion of high-density FPGAs. It operates with a 725-MHz toggle rate and delivers sub-4-ns clock-to-out times to match the the leading FPGAs. Power consumption is 0.32 µW/MHz/gate. A range of gate counts is available up to 2.5 million ASIC-equivalent gates. Designs at 2.5V and 3.3V are standard, and mixed-voltage designs are also available, such as a 3.3V core with a 5V tolerance.Each pad in the arrays can be individually assigned as an input, output, bidirectional, power, or ground for full pin-out compatibility with the FPGA. Pads can also be designated CMOS or TTL while offering 5V compatibility.