Electronic Design

Hardwired FPGA Option Shrinks Chip Size And Cost

Dubbed HardCopy, these hardwired versions of Altera's Stratix FPGAs double the performance of the SRAM FPGAs and shave 30% from the chip cost.

The large chip areas consumed by high-density FPGAs tend to make the devices rather costly for volume production. As chip size grows, performance likely decreases because wire lengths and parasitic capacitances increase as well. By creating a hardwired version of its high-density Stratix FPGA family, Altera Corp. offers an option that reduces costs by shrinking the chip size. The smaller chip area also pumps up performance and trims power consumption.

To support the design of a Stratix-based system, version 3.0 of the Quartus II design tools lets designers directly target a high-volume HardCopy device at the very beginning of the design process. Designers can verify timing, performance, and power estimates from within the design software, based on actual logic placement on the HardCopy devices.

Designers can then prototype a design using FPGAs. Once the design is finalized, they can transfer the configuration to a HardCopy equivalent, lowering cost by 30%, doubling the performance, and dropping power consumption by up to 40%. The tools provide the option of staying within the original performance achieved in the FPGA or boosting the performance by an average of 50%, or in some cases, by 100%.

The HardCopy Stratix FPGAs include all of the same features as the SRAM-based FPGAs—a hierarchical clock structure, the TriMatrix memory, and optimized embedded digital-signal-processing blocks. They also include all of the same high-speed interface options, like SPI-4.2, 10-Gbit Ethernet, and RapidIO. Also, the HardCopy devices are customized with only two metal-mask layers to implement the customer design, minimizing the nonrecurring engineering charges.

The five initial members of the HardCopy Stratix family range in density from 25,660 to 79,040 logic elements. Available in the company's FineLine BGA packages, they will range in price from $25 to $120 each in volume. The Quartus II Version 3.0 software costs $2000 and includes all system design tools, access to Altera's intellectual property portfolio, an advanced place-and-route engine that includes physical synthesis optimization technology, and comprehensive verification solutions. A free Web edition of the Quartus software is downloadable from www.altera.com/q2webedition.

See associated figure

Altera Corp.
www.altera.com/software

TAGS: Digital ICs
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