The 20-nm semiconductor process node promises tremendous power, performance, and capacity advantages for the next generation of electronic devices. At the same time, this upcoming process node raises significant new design challenges in such areas as lithography, complexity, and variability.
Success at 20 nm will require a carefully tuned, end-to-end design methodology that stretches from custom cell design to full-chip tapeout—and building this methodology will require deep and early collaboration among EDA vendors, intellectual property (IP) providers, foundries, and early-adopter customers.
Make no mistake—whatever you may hear about the challenges, 20 nm is coming. While it’s not yet in production today, foundries began aggressive 20-nm process development and investing in equipment more than three years ago.
Makers of mobile devices and communications infrastructure equipment have expressed strong interest in 20 nm. There are plenty of early adopters waiting to move to 20 nm. And over time, as foundries drive down the costs of this new process node, more and more OEMs will need to move there to stay competitive.
So what are the challenges at 20 nm? Perhaps the most discussed is the need for double patterning technology, which was not used at previous process nodes. When metal pitches shrink below 80 nm, as they will for lower metal layers in a 20-nm process, double patterning is needed to overcome the limits of existing lithography equipment.
Double patterning manufactures alternate tracks of metal in two separate steps. It requires extra masks, along with a colorized decomposition process that determines how layout features will be implemented by different masks.
Double patterning results in a number of layout constraints and advanced design rules, and it has a significant impact across the entire design flow. The impact is first felt in the custom design flow, where standard cells, memory cells, and custom layout blocks are created and where layout geometries that were permissible at previous process nodes may run into spacing or proximity violations because of double patterning.
The digital implementation environment must be able to read the double patterning “intent” embedded in the standard cells and macros. The placement engine needs to properly colorize cells and produce a placement that is both area-efficient and correct for double patterning.
Routing must consider double-patterning design rules and potential color conflicts beginning with the initial routing pass, rather than relying on a post-processing step to fix all the errors. The best routing approach is a correct-by-construction method, made possible by embedding physical verification within the router.
Another 20-nm challenge has to do with a key 20-nm advantage—the capacity for increased on-chip integration and complexity. Many 20-nm chips will have 100 million to 200 million gates, about twice the size of “large” chips at previous process nodes. Of necessity, most 20-nm system-on-a-chip (SoC) designs will consist primarily of externally acquired reusable IP, but even at an 80% reuse level there will still be a great deal of logic to design.
Functional verification, which by many accounts already consumes most of the IC design cycle, will become even more of a bottleneck. One solution is to design and verify at a higher level of abstraction using transaction-level models, high-level synthesis, and verification IP.
Timing and power variability were problems at 40 nm and 28 nm, but at 20 nm variability gets worse. Variability becomes more subject to layout-dependent effects (LDE), where the locations of cells and transistors that are placed near each other lead to variations in timing and power. No longer is it enough to know the characteristics of an individual cell. You also have to know what will be placed next to it.
Given all these challenges, some new tool capabilities are clearly needed. These include double-patterning and LDE-aware placement and routing. Further, EDA tools for 20 nm need to handle much larger capacities, driving the adoption of multicore platforms for applications that can be easily parallelized. And with wide variances in 20-nm processes from different foundries, design tools need to have as much built-in process “intelligence” as possible.
The most important point about 20-nm design tools, however, is that a traditional point tool approach will not work. What’s needed is a unified Silicon Realization methodology that goes all the way from standard cell and analog IP design in a custom layout system to physical design and full-chip signoff in a digital implementation system.
This Silicon Realization methodology requires a unified representation of design intent throughout the flow, the appropriate use of abstraction, and a rapid convergence into a manufacturable solution.
A unified, process-tuned design methodology will come about only through very early, and very deep, collaboration among major EDA vendors, IP developers, and foundries. For this reason, Cadence began working with multiple foundries on 20 nm three years ago and has collaborated on 20-nm test chips including a recently announced ARM Cortex-A15 chip taped out in cooperation with ARM and TSMC.
It takes a lot to ramp up a new process, including test chips, libraries, process development kits (PDKs), and fully qualified design tools. The industry is now well down that road for 20 nm, and very shortly consumers will be reaping the rewards.