Electronic Design
Know Your Mandatory And Recommended 20-nm Tapeout Requirements

Know Your Mandatory And Recommended 20-nm Tapeout Requirements

Centuries ago, mapmakers marked the areas beyond explored territories with the phrase “Here be dragons.” These days, EDA vendors talk as if 20 nm is the domain of dragons, and only by buying their products will you tape out a design, get to market in time, and profit. The “single-vendor strategy” marketing you hear from such companies may sound compelling at the 100,000-foot level. But when you face the challenges of 20 nm, common sense and practicality will be your best weapons.

So, what’s different as you move to 20 nm? The requirements for tapeout still will be broken down into two groups: mandatory, which are required for tapeout to your foundry, and recommended, which are highly recommended for optimizing design variability, performance, and yield. Like all prior technology node migrations, these requirements will be harder to implement at 20 nm. That said, 20 nm only will be incrementally harder, and the same rationale you used to select your EDA vendors at prior nodes is still appropriate.

New Technology Node Development

To introduce a production-worthy process at a new technology node, your foundry selects a reference EDA verification tool set to develop and characterize its new process technology for design rule checking (DRC), layout versus schematic (LVS), parasitic extraction (PEX), and fill. Results achieved by this suite of tools drive the reference that other EDA tools in the same category must match to be qualified for production.

Early in the deployment of a new technology node, there are constant changes to the verification requirements as the process is repetitively optimized based on the results of early test chip and design experiences. During this time, the foundry is continuously changing its process (and updating its design kits) to capture ever more subtle process effects to help minimize design variability, improve yield, and increase reliability. This stage is where 20 nm is now and is expected to be for a while.

If your market requires you to keep pace with the process implementation of 20 nm, using the same tools selected by your foundry as its reference enables you to incorporate these ongoing changes into your design and verification flows much more quickly. You can expect to experience the same results the foundry is seeing and receive more timely deck updates.

During early process development, it is very difficult for foundries to keep all EDA tools up to date, so there is a natural delay between the development reference tools and full ecosystem support. This issue is usually resolved when the general market goes to production in a process node. But for early adopters, the risks of using tools other than the reference tools for product design during new process development could include last-minute tapeout delays, or possibly errors that result in the cost and time delay of having to re-spin very expensive masks. Simply said, if you’re working early on in leading-edge technology and want to reduce risk, use the same leading-edge tools the foundries do.

Mandatory At 20 nm

There will be the normal organic growth in physical design rules and checks (see “While 28 nm Is Still Teething, 20 nm Will Be A Barrel-o-Monkeys”). Expect at least a 30% increase in the number of verification checks over what we have at 28 nm. Also, 20 nm will introduce more sophisticated and mandatory voltage-based DRC at the major foundries. Lastly, expect some foundry ecosystems to provide additional assistance through “yield detractor” pattern matching rules to support design optimization.

Double patterning (DP) is being introduced at 20 nm as part of the signoff DRC/DP deck. While the need for DP requires new checks and new types of design debug, DP checking only creates about 0.8% more DRC checks. These new checks allow the industry to make a practical move to 20 nm using the same process steps, avoiding the need to introduce another new variable—ultraviolet (EUV) or e-beam direct write (EBDW) lithography technologies.

Circuit verification and design for manufacturing (DFM) techniques such as litho-friendly design (LFD) simulation and fill must also consider how two mask layers are used to construct some wafer layers. Some industry observers claim that DP is the game changer and that because of DP, we are “at the edge of the earth.” The reality is that DP checking and the other new physical verification checks are more work, but no more so than moving to any new process node.

Using the same tools for your design signoff that the foundries use for their process development will ensure not only that you have the earliest access to these new rules, but also that you have the best opportunity to quickly incorporate them into your design and verification flows, while avoiding any correlation issues when your design is submitted to the foundry for wafer production.

Like DRC, LVS complexity will increase at 20 nm to support modeling challenges such as determining silicon stress effects and checking well proximity requirements. Parasitic extraction for interconnects will need to consider more complex geometric interactions and also account for the impact of double patterning, i.e., when a single mask layer design is split into two or more masks, creating additional sources of manufacturing variation.

Full-chip LFD hotspot checking is required for 20-nm signoff. The major foundry ecosystems are delivering solutions that combine pattern matching with LFD simulation to provide reasonable full-chip runtime performance.

Fill constrained by DRC density checking has been in practice for years. But instead of the polygon-based fill used since 130 nm, 20 nm will introduce a cell-based “smart” process that will be the new mandatory requirement for signoff at the major foundries. This new fill approach will help control file size and DRC run times while supporting the much more complex fill methodologies needed at 20 nm.

Recommended At 20 nm

The major foundry ecosystems are providing designers with an increasingly capable set of decks and utilities that help optimize the layout to rework patterns that are more susceptible to manufacturing variability. Examples include expanded recommended rules and design guidelines, recommended rule-driven design improvement/optimization decks, and DP debug hinting.

The foundry won’t require electrostatic discharge (ESD), electromigration, multi-domain power, or other reliability verification decks for 20-nm tapeouts. But with shrinking feature size designs, these decks do become increasingly sensitive to ESD. Recently, electromigration faults that went undetected due to inadequate checking have caused some very expensive and public product failures.

Many of these new checks look for design intent by analyzing design topology and perform targeted DRC checking on devices or nets of interest instead of checking all design polygons. With an increasing awareness of reliability-related issues, many design teams will consider these “recommended” checks mandatory, even if they aren’t on the foundries’ mandatory list yet.

Critical area analysis (defect sensitivity) checks have been in place for several technology nodes. They will play an increasingly important role in many design optimization flows because the size of the particles that cause random defects isn’t shrinking, but the line widths we’re trying to manufacture are.

20-nm Verification Flows

At each new technology node, a foundry or integrated device manufacturer (IDM) creates multiple experiments and processes wafers to fine-tune the requirements and constraints of the manufacturing process. Years are spent optimizing the process. Given the design data that foundries have access to, they do a good job creating and testing physical verification flows. But there are real opportunities for further improvement here.

In general, foundries don’t have access to large designs for the new technology node under development. This lack of access at a time when design-to-manufacturing process interactions are increasingly important can lead to surprises for early designs.

More three-way cooperation and collaboration between fabless companies, foundries, and EDA suppliers could help identify and characterize critical interactions earlier in the development timeline, shortening the time to process maturity and ultimately enhancing product quality. Naturally, this would require open sharing of design data, new EDA algorithms, and getting comfortable with constant change, but all ecosystem partners would gain from much more of this early cooperation.

Today, the reference flows publicly announced by the foundries are focused on single-vendor tracks (e.g., Mentor, Synopsys, or Cadence) that cover everything from implementation (custom design or place and route, or P&R) through design verification (DRC, LVS, DFM, etc.). But in practice, customers don’t generally use single-vendor flows. Rather, they create heterogeneous flows with multiple tools because no single vendor is best at everything, nor can one vendor meet all the needs of a given company.

Industry leaders generally use a heterogeneous EDA supplier flow, often selecting the best custom design tool from one vendor, the best P&R tool from a second vendor, and the best physical verification and analysis tools from a third vendor. During new node development, significant time savings could be achieved if the foundries also recommended best-in-class heterogeneous reference flows based on the tools most of the industry will actually use in production (i.e., best-in-class custom design, P&R, physical verification, circuit verification, and DFM).

Debug productivity and functionality also determine best-in-class tools. It’s one thing to find errors, but another to fix them. New debugging functionality, such as error/hotspot identification, hints for DP checking, and programmable electrical rule checking (PERC) interactive debug navigation for voltage DRC and other ERC checks are now available. In addition, advanced checking and result visualization functionality now can be accessed in the design environment through cross-vendor integrations with a variety of custom layout editors and P&R tools, providing signoff-quality debugging solutions during design and implementation.

Summing It Up

EDA marketing pitches imply that 20 nm is a completely new landscape and DP is a game changer. The reality is that, like all prior nodes, 20 nm is an evolutionary extension beyond the last node. There is more work to do, but the reference signoff tools used at prior nodes have the technology foundation needed to encompass and incorporate the new requirements at 20 nm (e.g., DP and voltage-based DRC). As usual, other toolsets will eventually include the necessary qualified functionality as well.

Use the same EDA tools your foundry uses. This will be especially critical early in the node, given the inevitable process churn. This gives you the same results as your foundry, as well as timely updates to decks, and prevents those last-minute correlation surprises.

Like the semiconductor capital equipment industry and hardware side of wafer manufacturing, schedule time to analyze and fully understand design, physical verification, and tapeout issues and how you can best adapt and optimize your verification flows. At advanced nodes, surprises lurk in the interactions between the design, the process, and your EDA flow. Plan now to spend the necessary time in preparation and education.

As sports teams the world over say, practice the way you will play. In setting up and preparing for the next node, put together the best-in-class EDA flow that will make you competitive, and then test with early prototype designs to flush out potential design and process issues and to learn how to use the new functionality needed to verify your 20-nm designs can be manufactured.

To maximize the value of your early testing, work closely with your EDA vendor(s) and selected foundry to understand the best implementation of the tools, optimization of the decks, and optimal application of each tool’s features and capabilities.

Design-to-manufacturing process interactions are where the “interesting” issues arise, regardless of whether you’re an early adopter starting 20 nm this year or adopting several years down the road. These issues can only be debugged in a timely manner with the exchange of data, test cases, and other information. Surprises are often found during a first tapeout, where the schedule is always tight, so schedule extra time before you begin. Put non-disclosure agreements (NDA) in place ahead of time so any issues can be addressed quickly without the inevitable delay of legal signoff loops.

Like prior nodes, 20 nm will have more than twice as many geometries and more than 30% more physical verification checks. EDA data processing is growing at an accelerating rate, and EDA tool core performance is improving. But to maintain or improve overall design cycle times, more hardware will be needed to maintain the turnaround time you had at the last node. Plan for the expense and installation ahead of time.

As was the case at prior nodes, 20 nm will see an increase in the breadth of manufacturing checking on new designs. Important new types of checking (like DP) will be required, but they are evolutionary, not revolutionary. Take the steps outlined to better plan for change, and you will find that your 20-nm dragons will become far more realistic and manageable.

TAGS: Digital ICs
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