The RTAX-S high-reliability, radiation-tolerant, space-optimized FPGAs provide designers with densities of up to 2 million equivalent system gates (approximately 250,000 ASIC equivalent gates). Created by Actel Corp., these arrays feature hardened registers that provide practical single-event upset (SEU) immunity. Also, usable error-corrected on-chip RAM is available for the first time. The FPGAs offer an alternative to custom-high-density ASICs to meet the density, performance, and radiation-resistance requirements of many satellite applications.
This family will fit in many of the bus and payload applications in low-, mid-, and geosynchronous-earth orbit satellites. Its initial members, the RTAX1000S and the RTAX2000S, offer equivalent system gate capacities of 1 million and 2 million, respectively, and 162 and 288 kbits of RAM. They have an inherent single-event latchup immunity and a greater than 37 MeV-cm2/mg SEU capability. Total ionizing dose performance exceeds 200 Krads. The chips' embedded RAM has an upset rate of less then 1E-10 errors/bit-day with internal error detection and correction.
Based on Actel's AX Axcellerator architecture, the RTAX-S chips present several architectural enhancements. There's an embedded FIFO controller, as well as a fully fracturable supercluster that allows for high logic-module utilization. A core tile structure provides tighter clock skew across the chip. That, coupled with a flexible clock structure that has eight global clocks available equally across the chip, helps reduce the need for clock floorplanning. To complement the arrays, Actel's designers developed some intellectual property that can be overlaid on the FPGA—a Mil-Std-1553B bus controller.
The lower-cost Axcellerator family of commercial devices can handle prototyping. Once the design is firm, the space-qualified devices, which sell for about $14,000 each, can be substituted.