Applications traditionally supported by high-density complex programmable-logic devices (CPLDs) and low-capacity FPGAs now have another option—the MachXO series of logic devices. Developed by Lattice Semiconductor, the family brings lower cost and more features to the table.
Lattice harnessed the efficiency of a logic architecture based on a lookup table and combined it with high-density, nonvolatile flash storage and distributed blocks of static memory. As a result, the MachXO devices shave cost by as much as 50% per logic function.
The MachXO series can handle many traditional FPGA and CPLD applications due in part to its on-chip distributed memory, a low-power sleep mode, and the ability to transparently update configuration data.
The logic fabric includes multiple 9-kbit, dual-port configurable SRAM memory blocks (embedded block RAM, or EBR) and analog phase-locked loops (PLLs) for precision clocking. The EBRs can operate at clock rates of up to 275 MHz and can be configured for width and depth. The memories will operate in single-port, dual-port, pseudo-dual-port, first-in/first-out, or ROM modes.
Handling frequencies from 25 to 375 MHz, the PLLs feature a low output-period jitter of ±125 ps and a programmable phase/duty cycle (adjustable in 45° steps). Their dynamic-delayadjust capability allows the edges to be adjusted in increments of 250 ps, with a total adjustment of 2 ns lead or lag.
Similar to the fabric in the company's XP series, the logic fabric consists of an array of programmable function units (PFUs) that each contain four logic slices. Each slice packs a pair of four-input lookup tables and the associated configuration SRAM. Such blocks perform logic, arithmetic, distributed RAM, and distributed ROM functions. Logic delay, including I/O pads, is typically just 3.5 ns, pin-to-pin.
A smaller version of the PFU—the PFF—excludes the configuration SRAM. As a result, it can only handle logic, arithmetic,-and ROM functions. Not all logic-functions require the RAM. By providing a mix of PFUs and PFFs, designers at Lattice improved the array's area efficiency and reduced chip cost.
To save system power, a low-power sleep mode can reduce the static supply current from about 10 mA to typically less than 100 µA. Therefore, MachXO devices should find homes in line-and battery-powered systems.
Flash memory stores all configuration data. Upon device power-up, a very wide internal memory bus transfers the configuration data to the logic fabric. Array configuration requires less than 1 ms.
With Lattice's TransFR configuration scheme, the flash data can be updated while the logic fabric runs the current configuration. After updating the data, it takes just 1 ms to transfer the new configuration to the fabric. This lets systems function almost nonstop.
Four devices make up the initial release—the MachXO256, 640, 1200, and 2280. The part number represents the number of on-chip lookup tables. The distributed RAM ranges from 2 kbits on the MachXO256 to 7.7 kbits on the 2280. The 256 and 640 won't contain any blocks of embedded SRAM. The 1200 has one 9-kbit block, and the 2280 packs three blocks.
I/O pads range from 78 on the smallest device to 271 on the largest. The larger XO devices will include PCI and low-voltage differential-signaling support. All I/O cells will support popular I/O standards such as low-voltage CMOS with 3.3-, 2.5-, 1.8-, 1.5-, and 1.2-V signal swings. There will be two versions of the MachXO family: the E series supports 1.2-V supply levels, and the C series packs an on-chip regulator to handle legacy supply levels of 2.5 or 3.3 V.
In lots of 250,000, the 256 and 640 cost $1.50 and $2.25 each, respectively. Samples are immediately available. The MachXO1200 will be released next quarter and the 2280 in early 2006. Lattice's ispLEVER design suite supports the series. It's available in Windows, Unix, and Linux versions.
Lattice Semiconductor Corp.