Electronic Design

Power Comes To The Fore In FPGA Design Environment

Power is a chief concern for chip designers, and those who implement their circuitry on FPGAs are no exception. Pressure is mounting to follow the crowd toward low power, but FPGA designers need comprehensive design flows geared toward achieving their power-budget goals.

Actel has stepped up with version 8.1 of its Libero Integrated Development Environment (IDE), which combines a pushbutton design flow and GUI wizards with power-driven layout capabilities (see the figure). One of the neatest features of this edition is its ability to create power profiles based on possible functional modes of the design.

Knowing that a cell phone is in sleep mode most of the time, users can plug in a sleep-mode value, say 90%. The tool reports on power consumption and provides battery-life calculations based on that value. A change in the sleep-mode estimate results in a corresponding realtime change in the power estimates.

The layout flow in Libero IDE automatically reduces power consumption by reducing the capacitance of nets within the design based on estimated activity. Unlike a timing-driven place-and-route flow, which will stop when timing is met with slack to spare, this IDE’s back-end flow continues to seek opportunities to reduce power even after timing is met.

Libero’s SmartPower analysis capability provides deep insight into how power is being consumed. Power-consumption reports can be broken down by logic, power rails, clock domains, and even hierarchy.

Libero IDE v8.1 is available now. The platinum edition for Windows or Linux platforms costs $2495. The gold edition for Windows is free. Both editions come with one-year renewable licenses.

Actel Corp.
www.actel.com

TAGS: Digital ICs
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