Electronic Design

Software Confronts New Yield-Management Paradigm

Yield analysis, a science formerly left to process engineers in foundries, is not a luxury any longer. According to Collett International’s research, at least 40% of designs face at least one respin with an associated delay of from four to six weeks. At least 22% of designs will see two respins, so make that delay 12 to 16 weeks. Some 60% of the issues causing these respins are silicon related. Let’s not forget that the new mask sets for each respin cost at least $1 million.

The 90-nm node represented a turning point in how fabless semiconductor houses and even integrated device manufacturers (IDMs) approached yield management. Before 90 nm, yield management was addressed in a “classic” fashion, with yield data analyzed for trends and statistical controls applied to the process. At 90 nm and below, the game changed, with many chip vendors adopting design-for-manufacturing (DFM) methodologies.

Now, at nodes of 90 nm and smaller, a new paradigm has emerged in the yield-management realm. It’s no longer only the process engineer looking for feedback from the yieldmanagement system. Faultanalysis engineers, test engineers, and layout engineers are all looking for more data with which to localize faults more accurately.

To address the needs of this newly broadened audience for yield-management data, Synopsys has launched Yield Explorer, which is billed as a “design-centric” yield-management suite. Yield Explorer aggregates data from lithography and Spice simulations, wafer-level and final-device test, manufacturing test, and any other form of custom data into one database.

It applies advanced statistical analyses and data mining techniques to enable distillation of everything from daily production trends to complex interactions between design, process, and test.

Yield Explorer also fits into existing design flows, taking in data from all steps (see the figure). That encompasses all design signoff steps as well as manufacturing-related phases such as mask data prep, test data, and diagnostics.

Yield-management data is not traditionally known to be design-friendly, so the challenge on Synopsys’ plate was how to lend a design-centric flavor to this kind of information. This was accomplished by making a layout viewer the core of the GUI, which takes users directly to failing cells in the design.

The GUI is augmented by a dynamically extendable database that doesn’t have to be set up for fabs. Users at fabless houses can organize data to see parameters of interest to them. Further, industry-standard automation is built in through tool command language (TCL) scripting. Standard scripts can be customized and passed on to less experienced users, relieving them from having to consult with a bevy of “experts” to get the job done.

A single Yield Explorer screen might display everything, such as wafer-level visualization of all failing dies or a roster of wafer-level statistics. Users can see spatial distributions across the wafer for the sorts of parameters found in scribe testing as well as in automated test equipment (ATE) tests. Another window might display corner-lot comparison analysis from Spice simulations.

Yet another can show correlations between yield and design attributes. For example, users can look at the overlap of a transistor on top of the oxide so leakage is controlled. Users can then plot the yield of that call as a function of the geometry by retrieving the geometry data from the design database.

Synopsys asserts that Yield Explorer will produce higher confidence in analysis results. Rather than just spitting out a list of failing cells, leaving the user to distinguish between random and systematic failures, Yield Explorer superimposes a wafer map of failing cells onto the results of criticalarea analysis and assigns them a physical defect-related failure score. Once random and systematic failure cells have been categorized, the low-yield wafers are further analyzed for cross-domain correlations that enable problems to be isolated to particular nets.

The bottom line is that yield management that traditionally has taken two to three weeks in a flow involving multiple manually driven tools (with multiple experts driving them) now can take as little as two to three days in a single-tool setting. The resulting physical failure analysis is also considerably more accurate, according to Synopsys.

For further information, including pricing and availability, contact Synopsys directly.


TAGS: Digital ICs
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