Once the prototyping and beta testing is done and a system goes into production, designers often will wonder: "With the higher per-chip cost of an FPGA, why not replace the FPGA with an ASIC?"
But the increasing costs of producing the ASIC, coupled with the reduced market lifetime of the end product (especially in the consumer market space), make it harder to justify the ASIC. And it's even more the case if the FPGA's performance can meet the application's needs.
Today, a new solution—the "structured" or "platform" ASIC—is entering the fray (for an overview of structured/platform ASICs, see Basics of Design, "Platform ASICs," electronic design, March 15). These alternatives provide an intermediate price point. They can lower the per-unit production costs versus an FPGA while keeping nonrecurring engineering (NRE) costs and turnaround time to one-half to one-third that of a full ASIC.
But the crossover point at which it becomes more economical to use the structured or full ASIC solution is shifting upward. In the past, most designers would agree that as volume usage crept past about 10,000 units, an ASIC solution made economic sense, especially if the product life was about two years.
Designers are now forced to re-examine the crossover point, with significant reductions in FPGA costs enabling vendors to sell megagate solutions for under $12 and 50k gate devices for under $3. Due to the NRE charges associated with an ASIC, it might take volumes exceeding 100,000 units or more before some type of ASIC alternative becomes financially attractive.
Furthermore, today's product life cycles are much shorter simply because of the need to continually introduce new features. SRAM- or flash-based FPGAs allow vendors to perform field updates to fix problems or add new features. Full ASIC turnaround times are typically nine to 12 months, so they don't fit the shorter product-life-cycle requirements. Structured ASICs, however, can trim turnaround times to just a few months, enabling them to replace the FPGA.
One example hails from Altera. Its Stratix HardCopy solution allows designers to quickly move a finalized logic configuration from an FPGA to the mask-configured lower-cost alternative. Moreover, for those designers seeking a structured ASIC solution, the HardCopy option can be used without first going to an FPGA implementation.