Electronic Design

System-On-A-Chip FPGAs Mix ASIC And Programmable Approaches

The LatticeSC family of system chips from Lattice Semiconductor melds some of the best features of ASIC technology and the flexibility of FPGA-based logic. This combination has yielded higher performance and more integration than previous FPGA solutions.

These field-programmable system chips (FPSCs) include high-speed serializer-deserializer (SERDES) channels. In turn, these channels support data rates up to 3.4 Gbits/s. Also on the chips are high-speed parallel I/O interfaces that can operate at up to 2 Gbits/s/pin and support a variety of differential and single-ended I/O standards (Fig. 1).

The chips offer flexible clock management structures and dense embedded memory blocks. Their FPGA logic can operate at up to 500 MHz. Special metal-mask configurable structured ASIC regions of about 50 kgates each have been reserved on the chips (up to 12 blocks on the largest family member). These regions enable the implementation of high-performance custom logic.

Known as Masked Array for Cost Optimization (MACO), these embedded structured ASIC blocks initially will be used to implement predefined performance-critical functions such as memory controllers, PCI Express interfaces, 10-Gbit Ethernet interfaces, and other functions (Fig. 2).

There will be two families of FPSCs. One family will come without the MACO blocks configured, and the other will come with the blocks preconfigured for 1- or 10-Gbit Ethernet, PCI Express, SPI 4.2, and DDR1 or DDR2 memory controllers. Five members have been defined for each family with from 15.2k to 115.2k four-input lookup-table (LUT) blocks and from 1.03 to 7.8 Mbits of embedded memory.

Eight LUTs are grouped to form a programmable function unit (PFU). Each PFU can be configured for logic, arithmetic, or distributed RAM/ROM functions. Additional resources include from 8 to 32 SERDES channels, four to 12 MACO blocks, and eight phase-locked loops and 12 delay-locked loops. Those resources are the same for both families.

The SERDES channels operate from 600 Mbits/s to 3.4 Gbits/s. They include physical coding sublayer (PCS) blocks. Also, they include transmit pre-emphasis and receive equalization features to support backplane drive lengths approaching 60 in. The flexible PCS blocks can be configured to support many popular protocols, including PCI Express, 1.02- or 2.04-Gbit/s Fibre Channel, Gigabit Ethernet, XAUI, serial Rapid I/O, and Sonet.

Embedded physical-layer functionality includes encoding/decoding, scrambling/descrambling, clock tolerance compensation, cyclic redundancy check generation/checking, and multichannel alignment. To handle the high-speed I/O signals, on-die termination helps minimize stub lengths.

First out of the ovens is the LFSC25, which packs 25,000 LUTs, 1.92 Mbits of embedded RAM, 16 SERDES channels, and six MACO blocks. It comes in a 900-ball fine-pitch BGA or a 1020-ball flip-chip BGA package. In lots of 25,000, the 900-ball version will cost $49 in 2007. A version with the MACO blocks configured will cost $10 premium more than the LFSC25. Lattice's ispLEVER version 5.1 design tool suite provides design support.

Lattice Semiconductor Corp.
www.latticesemi.com

TAGS: Digital ICs
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