The five mainstream FPGA vendors—Actel, Altera, Lattice Semiconductor, QuickLogic, and Xilinx—have a combined market share of approximately 98%. The remaining percentage points account for a few specialty suppliers that offer FPGA-like capabilities. All of these companies are fabless operations and rely on wafer foundries in Taiwan, Japan, Singapore, or Germany to produce their wafers.
As a consequence, they only have access to the technologies of their foundries, such as fast logic with SRAM capability or high-density floating-gate memory arrays. By leveraging standard process flows, FPGA companies can keep their manufacturing costs low.
However, Actel and QuickLogic worked in conjunction with the foundries to include proprietary antifuse technologies in the process flow. The antifuse technology provides some unique benefits: good security, small cell size, radiation tolerance, and, of course, nonvolatility. Still, it has one limitation. Unlike flash-based devices, once configured, the cells can’t be reconfigured (as is indicated by “fuse”). In addition, although the antifuse process is more complex compared to SRAM-based FPGAs, the cells are smaller, which results in smaller chips and lower cost for equivalent logic capacities.
For a long time, SRAM and flash technologies were mutually exclusive, i.e., they could not easily be integrated into one chip. Yet this scenario has changed thanks to recent developments in semiconductor technology driven by market demand. The smaller competitors (Actel, Lattice, and QuickLogic) now offer flash-based, single-chip FPGAs (the ProASIC, LatticeXP2, and PolarPro families, respectively).
Altera, for instance, has offered flash-based CPLDs (MAXII) since 2004, but currently doesn’t use this technology for FPGAs. Xilinx introduced its Spartan-3AN product line of flash-based FPGAs early in 2007, mounting two chips (FPGA and flash memory) in a single package, but doesn’t have a monolithic flash-based FPGA product.1 The ability to co-integrate the flash storage provides an improvement in IP security over the SRAM-based FPGAs, which use an external configuration memory, since it’s harder for someone to snoop the data transfer between the memory and configurable logic array.
One approach that meets all of these security requirements involves a challenge-and-response data exchange (authentication) between the FPGA and a secure memory. Secure-memory chips are an invention of the late 1980s. They became popular in Europe initially for payphone cards, and in the 1990s for bank cards, and are now a vital component in GSM cell phones (the SIM card). The prevalent communication standard between the secure chip cards and a host system is the I²C serial bus.
Custom-tailored for either banking or phone applications, secure memories weren’t considered viable for general-purpose use. This changed with the introduction of devices that incorporate the SHA-1 hash algorithm back in 2000 by Dallas Semiconductor (now Maxim Integrated Products). The first generation DS2432 was followed by the enhanced DS28E01. These devices use the 1-Wire interface, which serves for both communication and power supply. The DS28CN01, introduced in 2007, uses an I2C interface, but is otherwise similar to the DS28E01.
Another aspect to consider regarding IP security is the integrity of the foundries, since the foundries often have intimate knowledge of the FPGA design. Trust or strict control and supervision are necessary to protect proprietary information from getting into the wrong hands. This might be easier to achieve with domestic foundries than those abroad. Thus far, though, the major foundries have demonstrated excellent integrity in keeping design details under wraps.
References: 1. FPGA and Structured ASIC Journal February 27, 2007, “Short Stack with Syrup,” http://www.fpgajournal.com/articles_2007/pdf/20070227_stack.pdf.