VB-Verilog is an IEEE 1364-compliant Verilog simulator targeting the FPGA and ASIC markets. The tool provides uni-kernel and Open Model Interface capabilities, reflecting the industry’s increasing acceptance of reusable IP cores that are typically written in either VHDL or Verilog.The firm offers an open synthesis strategy with its tools, which currently interface with both Synopsys and Synplicity. VB-Verilog can simulate Verilog, VHDL or both in a common powerful, yet easy-to-use environment. The tool eschews the use of separate simulation kernels, which can negatively impact simulation speed and capacity. The uni-kernel approach provides a seamless environment.