Custom layout and place and route (P&R) tools historically have used internal design rule checking (DRC) engines to verify that a design passes basic DRC checks during physical design (see “The Traditional Approach To IC Implementation And Its Problems”). However, given the challenges cropping up at 45 nm and below, the industry must begin moving toward the use of signoff-quality DRC and design for manufacturing (DFM) engines inside all elements of their implementation flows. Designers, then, need to take a closer look at some of the requirements driving the need for full-featured signoff engines during design layout.
At advanced nodes, fill is no longer just a “check off” item on the production schedule. Fill solutions are getting smarter to accommodate the issues arising from the tighter spacing of advanced nodes—issues such as poly and metal density variation, multi-dimensional planarity interactions, and the impact of fill on timing (Fig. 1). The fill issue becomes more complex depending on whether or not the fab replaces the fill provided by their customers, using more sophisticated fill solutions that both prevent defects by maintaining better planarity and improve parametric yield by introducing less parasitic capacitance.
Fig 1. Complex fill algorithms can solve difficult fill challenges, such as multi-dimensional interactions between layers or density variation across a chip. Equalization-based fill can analyze interlayer density gradient and add fill to satisfy requirements across all layers (a). Density-based fill solutions can moderate changes between areas of high and low density using a minimum amount of fill (b). (courtesy of Mentor Graphics)
These smarter fill techniques provide density analysis concurrently with the filling operation to minimize the number of fill shapes added. New concepts such as multilayer fill shapes, non-rectangular fill shapes, and “fill cells” can simplify the creation of fill rule decks, improve the performance of the design, speed the filling process, and reduce the size of resulting GDSII files. Because density goals and analysis are included in the fill algorithms, the filling procedure is stopped when the layout meets density constraints, which include min, max, gradient, and magnitude. The goal is to achieve adequate fill density with significantly fewer shapes than dummy fill.
For the most demanding requirements, such a smart fill technology can also use thickness data from a full chemical-mechanical polishing (CMP) process simulation to determine an optimum filling strategy. Both approaches can impact parametric yield by reducing thickness variation impacts on resistance and capacitance added to the design due to fill. Intuitively, by filling smarter (i.e., with more advanced shapes and with an overall lower number of shapes), timing impacts are minimized, if not eliminated. Of course, actual results will change, depending upon the design style of different teams.
There has also been a great deal of discussion in the industry, particularly by the P&R suppliers, about whether timing-aware fill is needed at the 28- or 20-nm nodes. That is, is it necessary to incorporate final GDSII fill data into the extraction and timing analysis flow? If designers are contemplating the use of timing-aware fill, they will need to ensure they are using the final fill data that is actually used in manufacturing to have meaningful results and achieve accuracy in their timing analysis.
Just as the foundries are moving beyond dummy fill to improve margins and ensure high manufacturing yield, designers must also start using these same advanced fill techniques during layout implementation, as there are contextual impacts due to placement of hard intellectual property (IP). This requires intimate discussion with the IP developers, be they within the same company or a third party.
As we push further beyond the previous limits of sub-wavelength lithography, geometries around the primary shape being checked now influence whether or not a DRC error occurs. In other words, context now matters (Fig. 2).
Fig 2. At 45 nm and below, design constraints and influences extend far beyond simple length/width measurements. (courtesy of Mentor Graphics)
Being able to recognize and avoid using known problematic shape configurations throughout a layout can be crucial to manufacturability at advanced nodes. Foundries are now establishing libraries of patterns known to be yield detractors and have begun adding pattern matching against these libraries to their signoff requirements. For the design houses, that means that part of the DRC process now will be the identification of specific problem patterns contained in the foundry’s library. Some design houses are also establishing their own proprietary pattern libraries, which go beyond those provided by the foundry, to create or maintain market advantage through better performance or higher yield.
The tooling required to implement this methodology includes a pattern detection engine that can search an entire layout and identify all patterns of interest. This engine must allow for some error margin in the pattern geometry (to prevent false positives) and be very fast (so as not to slow down design creation). The designer also needs complementary tools to create and extract patterns and to modify them as needed. None of these capabilities are provided, or are likely to be provided, by DRC checkers built into custom layout and P&R tools.
Integrating pattern matching technology into the layout implementation process enables designers to recognize and eliminate any use of these patterns early in the layout flow, before the layout becomes more difficult or impossible to adjust. As pattern matching is added to the list of tapeout requirements imposed by the foundries, it also becomes mandatory. Using a signoff-quality DRC engine that incorporates pattern matching capabilities is the logical path for design houses to follow.
Foundries have long relied heavily on process simulation (model-based) tools, such as lithography and planarity simulators, to predict design failures resulting from specific process conditions (Fig. 3). They are now beginning to mandate the use of these models as part of their design signoff requirements, just as DRC has been for years.
Fig 3. Process simulations, such as planarity (left) or lithography (right), can predict design hotspots that may result in manufacturing failures or performance limitations. (courtesy of Mentor Graphics)
With foundries imposing more pre-tapeout requirements, design houses that are not implementing model-based DFM as part of their design flow may find themselves seeing unreasonable variations in yield or performance issues that occur as a result of design conditions that could have been identified before tapeout.
Double patterning has been identified as an enabling technology at 20 nm and below, meaning designers must be able to analyze their designs for both patternability (whether or not a single layout structure can safely be decomposed into two masks) and composability (whether or not combinations of configurations in a complete layout remain decomposable).
The complexity of these technologies, and the tight correlation they must maintain with foundry data and processes, suggests that gaining access to the foundries’ models and simulations during design implementation is an effective way to ensure concurrence between tapeout and manufacturing results. This implies that designers are better off using the same signoff tools used by the foundries to ensure concurrence between design layout checking and silicon results and provide full comprehension of the certification process the foundry has for various tools.
With many more checks, and more complicated checks at advanced nodes, designers now have to analyze and fix significantly more difficult errors while still maintaining tight design development schedules. Providing critical information to help designers understand both why an error occurred and how it might best be fixed is one way to reduce time spent debugging and correcting layouts (Fig. 4).
Fig 4. Full-feature DRC/DFM engines can provide designers with a variety of information and automated assistance during debugging and error correction. (courtesy of Mentor Graphics)
With access to a full-featured DRC engine, designers can take advantage of such advanced capabilities as equation-based DRC to obtain precise information about the error condition and the necessary correction, as well as pattern matching to identify known problematic configurations. In addition, evaluating layouts against a qualified recommended rules deck enables designers to identify and improve areas particularly susceptible to manufacturing defects.
Debugging assistance can take the form of correction hints, hotspot identification, suggested optimizations, or even visual clues that help determine when the correct configuration has been achieved.
Custom Design Debugging
Using industry interfaces such as the OpenAccess Run Time Model, it is now possible to embed a signoff-quality DRC/DFM engine in custom design tools to run design rules checks in real time. This provides immediate feedback on each shape as it is incorporated into the layout. With this increased speed, such an environment can even provide visual cues that show the designers where a shape can be placed, or how dimensions must be optimized, during drawing. This can give designers more time to implement design optimizations while still meeting time-to-market schedules.
P&R tools that incorporate full-featured DRC/DFM engines not only ensure more accurate checking, they also can provide automated fixing solutions driven by the actual signoff rules and the full range of complementary technologies, such as lithography simulation and planarity simulation, to deliver “correct by construction” layouts based upon a design team’s techniques. This will never be a “one size fits all” situation, because with multiple companies targeting the same process, differentiation must come from the design. Regardless, for this to be a practical solution, the DRC engines must be extremely fast and tightly integrated into the design for instantaneous access to the design database.
The three most important words to a design house should be accuracy, accuracy, and accuracy, because the discrepancies that occur between the design team and the foundry have a huge impact on schedules, successful silicon, profits, and careers. It is now possible, and increasingly necessary, to address the range of issues found in advanced node designs using the latest foundry-qualified DRC and DFM technologies at the earliest point in the implementation flow, whether for custom or P&R implementations.
By adopting tools and technologies that match those used by the foundries, design houses can ensure that the results that they obtain at tapeout will satisfy the foundries’ manufacturing requirements. Bringing fast, signoff-quality DRC/DFM into the design implementation means fewer full-chip iterations, faster debugging and error correction, and ultimately better designs because the time saved on verification can be applied to design optimization without impacting production schedules.