Electronic Design
While 28 nm Is Still Teething, 20 nm Will Be A Barrel-o-Monkeys

While 28 nm Is Still Teething, 20 nm Will Be A Barrel-o-Monkeys

It’s time to reflect on what the world will have in store for us in 2012. If you were a time-traveling Mayan, I suppose you might say “the end is nigh.” I don’t think it’s quite that desperate. There will be lots of challenges, but the industry has also made some real progress in preparing for the coming technology nodes.

28-nm Technology Node

As with the production ramp of the 45/40-nm technology node, the 32/28-nm technology node is still undergoing teething pains. Though the yields are far lower than desired, 28-nm designs are being successfully manufactured. With these low yields, many more wafers are needed to produce the desired number of good die, putting capacity pressure on the manufacturers/fabs.
 
Expect to see yields improve in 2012, taking some pressure off capacity, and just in time, as the number of 28-nm design completions is forecast to increase by as much as 50% over 2011. Because of this tight capacity, some of the biggest fabless/fablite companies are aggressively looking at moving some manufacturing to secondary foundries to ensure they get the quantities of die they need to meet consumer demand.
 
The manufacturing issues of 45/40 nm were largely addressed by additional design rule checking (DRC) checks. Between the early DRC decks at 45/40 nm, and those decks today with stable manufacturing, the industry added an average of 900 DRC checks. In 2012, expect to see an analogous increase in 28-nm DRC checks as the foundries improve their understanding of yield-limiting design attributes.

20-nm Technology Node

It’s still the early days for 20 nm, with 2012 seeing approximately 30 design “completions” (a.k.a. test chips) during the year. By most accounts, the first real design tape-outs for 20 nm are expected to occur in 2013, and 20 nm will bring some interesting changes in how designs are verified and manufactured.
 
Scanner resolution improvements have stalled at the 193-nm wavelength using immersion lithography—sufficient for 28-nm IC designs, but not beyond. Double patterning (DP) is the solution the major foundry ecosystems are using now to manufacture 20-nm IC designs.
 
The concept of DP is simple—simply split design layers where structures are too close together to resolve with 193-nm lithography into two separate masks, expose each mask separately, and the resulting geometries produced on the wafer will be what was originally drawn.
 
Manufacturing constraints have been captured as DRC checks for decades. To the designers, DP is simply more of the same, increasing checks by about 0.8% for the typical 20-nm DRC deck (roughly 30 new checks for DP out of an expected 3800 checks).
 
In addition to new DRC checks, the move to DP will require some changes with design for manufacturing (DFM) technology, such as litho-friendly design (LFD) simulation and fill, and in-circuit verification like parasitic extraction (PEX). In the era of DP, LFD simulation will need to be performed on the DP decomposed mask layers.
 
Fill will see some interesting changes in 2012. At 28 nm, we have seen an explosion in fill shape counts and the need for ever more complex fill structures and control. Instead of the polygonal-based fill used since 130 nm, 20 nm will introduce a cell-based “smart fill” technique, which will be mandatory at the major foundries. This new fill approach significantly reduces file size and DRC run times. It also supports the much more complex fill methodologies required at 20 nm, such as density balancing across the DP mask layers.
 
For PEX, DP requires additional corners, driving the need for accurate, fast extraction on multiple CPUs—critical to ensure good turn-around time (TAT) for timing closure. Given the size of the designs expected at 20 nm in 2012 and the years following, multi-CPU scaling to reduce extraction TAT will be a key market driver in this space.

Multi-Domain Power

Smaller nodes mean thinner gate oxides. Coupled with design trends where customers are employing a multi-power domain strategy (low VDD for digital, higher VDD for analog, potentially high voltage for certain applications), this means designers will need to rigorously check their circuits to avoid structures that can result in delayed electrical failure.
 
As an industry, we have developed new circuit verification techniques that will see broad use across multiple technology nodes. Initial introductions were seen with the foundries in 2010/2011, and we expect to see broad deployment in 2012.
 

2.5D/3D-IC

 
The new year will bring more growth to 2.5D-IC. During 2011, we saw press releases on the promise of 2.5D/3D-IC and a couple of isolated chips like the Xilinx Vertex-7 FPGA. EDA companies are working with multiple design companies and the major foundries to bring silicon interposer-based (SiI) 2.5D-IC designs to production next year.
 
Although forecast by some to only be available a short time (until such time as die-on-die stacked 3D-IC is available), expect to see SiI-based 2.5D-IC designs for years to come. Early applications will directly link memory with large GPUs, CPUs, and systems-on-a-chip (SoCs), using the SiI to address the memory bandwidth limitations of current approaches.
 

Summary

 
It should be a very interesting year. We should see 28 nm mature beyond its teething pains and start the march toward becoming mainstream. Many of the top 20 IC design companies will begin their forays into the DP world. DP will bring changes in how designs are verified and manufactured, but to most designers, the changes will be modest. The major issues have already been addressed by new cell libraries combined with the signoff tools they relied upon at prior nodes.
 
This year will also see growth in multi-domain power designs and verification. Finally, we will see 2.5D/3D-IC beginning to move beyond the hype phase to deliver real designs. It should all be fun, as long as the Mayans were wrong about that whole “end of the world” thing.
 
Michael White is the product marketing director for Mentor Graphics’ Calibre Physical Verification products. He received a MS in engineering management from the University of Southern California MBA School and a BS in system engineering from Harvey Mudd College.
TAGS: Digital ICs
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