Copper backplane interconnects, struggling to meet the needs of high-speed backplane communications, are presently stuck at about 10 Gbits/s. In fact, most systems work at just 3 Gbits/s. To go any higher requires more complex and costly optical interconnects. Nevertheless, copper cables, particularly coaxial cables, have shown that they're capable of higher backplane data rates and can serve as excellent transmission media. On the downside, there are interconnect and channel losses incurred going through a connector.
Recognizing these limitations, SiliconPipe, San Jose, Calif., came up with a novel backplane technology that allows coaxial cables to carry data at a projected rate of 40 Gbits/s. The company's ChannelPlane technology, code-named Yosemite, has reached speeds previously thought to be unattainable using copper. To top it off, costs are projected to be lower than today's 3-Gbit/s backplane technology.
To develop this new technology, SiliconPipe drew on its experience in other high-speed interconnect technologies. It currently offers the 20-Gbit/channel chip-to-chip Sequoia interconnect technology, and the 12.8-Gbit/channel Grand Canyon memory-channel technology. An implementation of ChannelPlane, the CP-OC768, is already being used in a patent-pending Yosemite-HPSP (High-Performance Signal Path) trace and via replacement system.
"If we provide a system with the transmission properties of high-performance coaxial cables, we can achieve 40-Gbit/s transmission rates per channel," says Thomas Obenhuber, SiliconPipe's vice president of marketing.
The solution lies in the company's approach to the interconnect problem. Instead of relying on a conventional backplane connector scheme, engineers created a backplane system that allows the coaxial cable conductors on one side of the backplane to mate "head on" with existing conventional backplane connectors (Fig. 1).
DEFINING THE PROBLEM
Conventional backplane connectors use a "prong and sleeve" approach: One cable connector that enters into the backplane contains the male prong pins, and the other comes out of the backplane with female sleeve jackets, into which the pins slide. This approach degrades the signal because it introduces interconnect losses that consist of resistive losses and a lack of uniform impedance, as well as channel losses. Channel losses include dielectric, conductor and fringing losses, which combine to act as performance bottlenecks (Fig. 2).
High-speed backplanes built today are limited in bandwidth by the materials and design of the system's interconnects. At high frequencies, attenuation and reflections degrade the signal. These discontinuities in the signal path limit the transmission of high frequencies and increase signal rise times. This, in turn, causes intersymbol interference, deterministic jitter, and collapse of the eye diagram.
Designers can use certain techniques to control fundamental signal-transmission limitations in conventional backplanes. These include the use of low-loss laminates, stub back-drilling, and active signal-conditioning techniques. But these come at a price that increases the cost of backplanes and line cards.
SiliconPipe's solution eliminates the male and female socket with a sexless interface at the end of the cable. The only performance-affecting part is a compliance interface. SiliconPipe designed this interface to be less than one-quarter of a wavelength thick, with controlled impedances and consideration for fringing, effectively eliminating performance-limiting discontinuities when using conventional male/female backplane connectors.
The proof of the interface's high-level performance can be seen in the excellent eye diagram (Fig. 3). At the time of this writing, SiliconPipe obtained this diagram (in collaboration with one of its component partners) while testing its backplane at 10 Gbits/s. A test setup at 40 Gbits/s is underway, and its results will be released shortly.
Because no media discontinuities exist in the ChannelPlane system, there are no vias or stubs that cause degradation of the signal. All signals are routed straight from the surface of the ChannelPlane, known as the XL array, keeping impedance mismatches well within the range of 100 Ω (±3%) under all conditions.
There's no great magic in the choice of a coaxial cable or a mating connector. SiliconPipe uses a W.L. Gore coaxial cable on one side of its backplane and an SIP 1000 Winchester connector to mate with the backplane on the other side. Therefore, many standard high-speed connectors from industry leaders like Teradyne, Winchester Electronics, and Tyco Electronics can also be used to get the same performance. Up to 95% of such connectors are 2-mm types that are limited to transmission speeds of 5 Gbits/s when used in conventional backplanes.
IT'S IN THE DESIGN
The key is in the design of the backplane connection system. It contains two mounting holes to ensure that whatever connector is used, it mates "head on" with the other connection part containing the coaxial cable pins. Pin positional accuracy can be within 2 mils, easily achievable with standard pc-board manufacturing processes.
The backplane interface consists of a 184-pin Winchester connector that handles 46 differential pair signals. SiliconPipe's XL array connector design has greater than twice the density of the Winchester connector. Because the cables mate head-on with the connector, there's no need for routing channels, as with all other connectors. This allows for 160 channels of signals, each operating at 40 Gbits/s, in a 1 in.2 area.
The ChannelPlane system consists of two major components: a reduced-layer FR4 backplane containing power, ground, and low-frequency signals; and an integrated Omnibus system, which carries all high-speed links over high-performance cables. The ChannelPlane system can be expanded to become a uniform connection from IC packages on one line card, through the backplane, to IC packages on another line card, for optimal system performance. Package connections that eliminate discontinuities in line cards are made close to the silicon die, using low-loss interconnects. Discontinuities from vias, multilayer pc-board traces, and IC substrates are eliminated.
While SiliconPipe hasn't put a specific price on its ChannelPlane system, the company contends that it will be competitive with much lower-performance systems. "Manufacturing costs are similar to those of high-density backplanes. This means 40-Gbit/s performance at the cost of 3 Gbits/s," explains Bill Wiedemann, president and CEO of SiliconPipe. "Our technology is essentially a quantum leap in backplane performance at the price of today's technology."
The ChannelPlane technology is available for customer designs in 30 days. System-verification quantities will come within 60 days of selection.
For more information, contact SiliconPipe at (408) 282-3700, or visit www.siliconpipe.com.