The dizzying pace of semiconductor IC miniaturization and performance advances keeps changing the face of IC packaging. Demands for lower-cost packaging that must also deal with greater amounts of heat emanating from these tinier packages have designers scrambling. Many packaging efforts are being devoted to materials innovations that optimize the existing manufacturing infrastructure.
Variations of the popular package-on-package (PoP) and package-in-package (PiP) approaches for consumer electronics products are emerging. These include the fan-in PoP (FiPoP) that combines the benefits of both PoP and PiP packaging, and flip-chip PiP (fcPiP), which allows the marriage of wire bonding to PiP packages.
Flip-chip technology benefits from an important development coming out of Engent Inc., a spin-off of the Georgia Institute of Technology. A new void-free hybrid no-flow process was developed for flip-chip underfilling to improve reflow process characterization and increase device reliability levels (Fig. 1). Some 2000 air-to-air thermal cycling tests of devices demonstrated exceptional reliability levels without any electrical failures.
Wafer-level packaging, the fabrication of the IC package directly on the wafer, is gaining greater acceptance from the IC semiconductor industry. It’s paving the way for 3D ICs and MEMS devices.
Although wafer-level packaging technology holds promise for memory and CPU chips, it must solve thorny challenges for large chips that exhibit high thermal coefficient of expansion (TCE) mismatch characteristics between the chips and the substrate they’re mounted on before it can be used more widely. Better burn-in and test/handling procedures also need to be developed.
In the world of high-performance microelectromechanical system (MEMS) ICs, which involves moving devices, environment-resistant wafer-level packaging is often a must. This is particularly true for navigation-grade gyroscopes and oven-controlled crystal oscillators. ePack, a spin-off of the University of Michigan’s Center for Wireless Integrated Microsystems (WIMS), developed a generic packaging platform for these types of MEMS devices. It involves packaging individual MEMS devices in a vacuum (<10 mTorr) and allows for temperature control of less than 50 mW and vibration isolation (Fig. 2).
Thermal and mechanical isolation are achieved simultaneously using glass isolation suspensions. The suspensions are stiff enough to support the platform and withstand shock and vibration, but also flexible enough to provide thermal and vibration isolation. A thermal impedance of 3000K/W is achieved, corresponding to power consumption of 43 mW, when the platform is oven-controlled at 85°C and the temperature of the external environment is –50°C.
One of the leaders in 3D ICs is Ziptronix. Its patented ZiBond CMOS low-temperature covalent bonding and direct-bond interconnect (DBI) processes “will enable true 3D integration of semiconductors for a host of products like mobile phones, PCs, video games, pico-projectors, automotive sensors, and medical imaging systems,” says Dan Donabedian, Ziptronix’s CEO. The DBI process is scalable to a pitch of less than 1.0 µm with improved alignment and placement tools.
Keith Cooper, business development manager for Suss MicroTec, believes that metal eutectic bonding will be an enabler of next-generation MEMS devices that require a high level of performance. Characterized by the direct transformation of the mixture of solid alloys into a liquid phase, eutectic metal compositions offer several benefits as sealing materials, says Cooper. These include the ability to accurately deposit and define metals in desired patterns, and tolerance to surface deviations, roughness and particulates, and hermeticity and conductivity.
A major challenge for using 3D integration is recognizing those specific applications that warrant it. According to Michael Shapiro, senior technical staff member of IBM’s Systems and Technology Group, in microprocessors, the motivation for going the 3D route is to add multiple cores and increase the amount of level 1/level 2 (L1/L2) cache memory. This allows for a smaller chip size and the housing of multiple cores in a single package. In addition, on-chip interconnection lengths become smaller, mitigating parasitic effects on signals.
A notable advance in packaging comes from Finland-based Imbera Electronics. It allows the embedding of discrete components inside an organic low-cost motherboard or substrate. The third generation of the IMB (Integrated Module Board) technology provides a flexible platform for multiple component types, from low to mid-range I/O counts. It essentially fuses component packages to the substrate. The manufacturing process combines a number of separate production phases into a single process, enhancing overall efficiency and offering a wide range of capabilities (Fig. 3).
Using through-silicon vias (TSVs) for interconnects in 3D packaging is making serious inroads. For many ICs that include MEMS devices, wafer-level bonding for first-level packaging—combined with the use of TSVs—is widely regarded as the next enabling technology for the semiconductor IC industry. The first step in this evolution is to adopt the proper metal-bonding methods that are compatible with first-level packaging, as well front- and back-end fabrication methods.
However, many more aspects of TSV development still must be settled by the semi industry. TSVs, for example, can be implemented by stacking wafers atop wafers, or stacking single or multiple dice on wafers, Then there’s the matter of wafer size, via thickness (to minimize wafer thinning), the right plating process, how to fill the vias and with what materials, wafer bonding, and a host of other issues. All of these matters are undergoing thorough analysis by semiconductor equipment and materials suppliers.
The Semiconductor 3D Equipment and Materials Consortium (EMC3D) is pushing for partnerships among equipment and materials companies in developing TSVs. The objective is to reduce development costs for individual companies.
One such collaboration involving EMC3D member Semitool and other companies has demonstrated a smoother TSV process flow. The work involves optimized via filling by adjusting plating chemistries for more uniform fill and less oxidation. The proprietary iTSV process uses a via-first chip-stacking approach with 5- by 30-µm via feature sizes.
According to Rozalia Beica, Semitool’s TSV director and program manager of EMC3D, the process methodology and feature sizes were selected because of the etch and deposition challenges they present and the interest and customer requests for a cost-effective solution. She explains that the process is available at a cost of $189 per wafer, for a 10,000 wafer/month capacity line. The objective is to bring cost down to $145 per wafer sometime this year. This drops well below the $200 per wafer cost of ownership goal over a three-year lifetime set by the EMC3D about two years ago.
Another EMC3D member, the EV Group, developed a hybrid bonding method that allows for cost-effective 3D TSV die-to-wafer processing (Fig. 4). The company slightly modified an original pure copper-to-copper thermo-compression bonding method by including an additional patterned and compliant tacky polymer glue layer between the dice. This method stabilizes the extremely thin top die after bonding and carrier release, as well as supports the stacked die in areas where little or no electrically functional interconnections exist between the dice.
Suss MicroTec introduced a wafer bonder, the XBC300, specifically designed for 3D 300-mm wafer bonding of CMOS image sensors using TSVs. Also, Toshiba announced a VGA CMOS image sensor manufactured on a TSV process. By using TSVs, Toshiba reduced the size of the sensor’s image module housing by 73% compared to a wire-bonded version.