The push for 3D packaging of semiconductor ICs directly results from market demands for smaller and lower-profile, lighter, and lower-cost packaged ICs that consume less power. With such market forces at play, package designers are feeling the strain to keep pace with their IC chip designer brethren.
For several decades, IC designers could leverage the advantages of a silicon die's planar area (the X and Y directions) to define and pack in more transistors and gates. Getting the most functions possible on a single planar piece of silicon is the everlasting goal for IC designers. That model is changing, though, and it's often a myth for many consumer electronics applications.
As line geometries shrink to 40 nm and beyond, critical issues like higher costs and a greater need for thermal management raise their ugly heads. Moreover, the development of system-on-a-chip (SoC) ICs packed with ever-more functions on a single planar chip is becoming prohibitively expensive. Thus, there's a push toward leveraging a silicon die's third dimension, the Z axis, to satisfy mass-market applications in the consumer, automotive, and medical electronics fields, particularly for portable devices.
During the 1990s, small-footprint IC package creation began with the development of the thin small-outline package (TSOP), followed by the chip-scale package (CSP). The last few years have ushered in multichip packages (MCPs) and system-ina-package (SiP) concepts (Fig. 1). An MCP holds two or more IC die in one package. An SiP combines an IC die with other components in a single package.
Though MCPs and SiPs constitute a small part of the overall IC package market, they're growing in market share. Market research firm IC Insights says MCPs will grow at a compound annual growth rate (CAGR) of 12% through 2009, and SiPs will grow at a CAGR of 14.6% through 2009. These growth rates exceed the general growth rate of all IC-package types.
The cell phone is the most significant 3D-packaging application. Nokia expects an annual 20% drop in weight and overall size for cell phones over the next few years, ratcheting up the pressure. The company also predicts the overall number of cell phones worldwide to expand to 740 million units by year's end, compared to 643 million units last year.
Digital cameras, another major driver for 3D packaging, use the SiP approach. "Key technology drivers for the SiP approach are the use of x32 double-data-rate (DDR) memory devices with high-speed buses, an increase in memory capacity, and the integration of all-memory chips with logic for lowend products," says Tom Gregorich, senior director of IC package engineering for Qualcomm.
Other consumer electronics applications for 3D packaging include digital camcorders and DVD players. A number of consumer electronics items employ the CSP approach. In a CSP, silicon dies are stacked on top of one another within a single package. The dies contain memory devices such as flash and static RAM, as well as logic devices.
A CSP performs at a higher level than the previous-generation TSOP. It can handle signals well beyond the 400-MHz limit of TSOPs and features shorter signal delays. Tessera has pioneered many CSP advances, such as its m Z ball-stack technology. Up to eight m Z ball-stacks are possible for DDR2-type memory.
Tessera also developed a lowerprofile CSP for RF wireless handsets, which compares favorably to a ball-grid array (BGA) package (Fig. 2). It uses coplanar pins on a compliant substrate, enables the use of 300-mm fine-pitch devices, has improved electrical performance, and doesn't require a testing socket interconnect. Simple pressure contact to the pc board is all that's needed.
DEFINING A 3D PACKAGE
Several notable approaches were made to realize 3D IC packaging. Yet there's some confusion over defining such a package. The 3D purists argue that a true 3D IC package holds a monolithic IC with multiple layers of interconnected silicon devices in the vertical direction.
Such an approach starts from the front end of an IC process. It differs from conventional so-called 3D packages that essentially stack chips and ICs at the back end of a process. Those purists argue that while back-end process approaches may provide small-footprint and high-density advantages, they're challenged by higher costs (due to fewer known-good dies, or KGDs) and thermal-management issues. Front-end-based approaches don't face such challenges.
Matrix Semiconductor fashions itself as a developer of a true 3D packaging concept with its 3D memory products. The company claims that its approach means a much smaller die for a given density than other approaches, resulting in significant cost-per-bit savings (Fig. 3).
Nevertheless, stacking memory and logic die as well as packages is the norm for many consumer electronics applications. Stacking dies of mixed functions like memory and logic is more challenging than stacking dies of memory alone, because memory chips generally have higher yields than logic chips.
Some packaging experts use package stacking as an alternative. Memory packages and logic packages are stacked on one another, mitigating some of these problems. Meanwhile, three primary options exist for the SiP approach: die stacking, package stacking, and module stacking (Fig. 4).
Spansion LLC, the flash-memory venture of Advanced Micro Devices (AMD) and Fujitsu Ltd., came up with an innovative package-on-package (PoP) solution as an alternative to the SiP. This approach allows for easy stacking of standard memory and logic packages and offers a shorter time-to-market. There's also greater flexibility at a tradeoff of a slightly larger planar (X and Y axes) area, caused by the need for memory packages to accommodate more logic package land points.
Jeremy Werner, solutions delivery marketing manager for Spansion's Wireless Systems Division, is confident that the PoP approach will be the next 3D packaging development for highdensity memory chips. Spansion can deliver eight-die memory products in a 128-ball, 12- by 12-mm (or 15- by 15-mm) package with a 0.65-mm pitch. In addition, the company's R&D in NOR flash-memory technology has led to breakthroughs such as its MirrorBit technology (Fig. 5).
Amkor Technology sees lots of customer interest in combining its PSvfBGA high-density bottom logic package with Spansion's PoP approach. The PSvfBGA reduces the routing density and component area required in the underlying motherboard, forming an interconnect foundation for the entire PoP stack (see the article's opening photo).
Another 3D-packaging method is the package-in-package (PiP) approach used to package DRAMs. Here, two or more packages are assembled together and overmolded, resulting in a single package that interconnects to the product board (Fig. 6).
One intriguing 3D-packaging method tries to improve die interconnect technology, making it more cost-effective to use a multidie stacking approach. Research is under way at several companies and groups involving multidie designs that are transparent to the packaging engineer. This is achieved by vastly increasing the number of die interconnects while slashing interdie delays. Belgium's Interuniversity Micro-Electronics Center uses through-die vias, around-the-edge interconnects, and bump layers on both faces of the die to build stacks of dies with interconnect sites all through each stack.
"There's a twofold challenge to improving die stacking, which is the most prevalent 3D packaging method," says Craig Mitchell, Tessera's vice president of marketing. "These include increasing the number of dies being stacked, which affects yields, and simplifying the assembly process resulting from complex wire layouts and connections."
As 3D packages shrink and pack more functions, it becomes imperative for 3D design-automation tools to be used early on in the chip and package design cycles to analyze electrical, mechanical, and thermal effects. Felicia James, vice president for Cadence Design Automation's Virtuoso platform, emphasizes "the importance of being able to capture real-world effects early on in the design process, such as analyzing 3D effects in the context of the overall design simulation." Increased co-design and knowledge sharing among IC and package designers is essential to further improve miniaturization and integration efforts.
An Yu Kuo, CTO for design-automation tool company Optimal Corp., is even more specific on this point: "Instead of evaluating signal integrity, power integrity, and thermal characteristics of devices on a package in just the 2D plane, designers must be able to account for these issues from all angles, including the 3D perspective using 3D EDA tools."
Thinner encapsulant materials, composite substrate materials, and ultra-thin wafers demand better analysis using EDA tools. Differences in thermal expansion for these materials and careful control of the molding process temperature used in packaging is mandatory. Package warp and die warp pose two mechanical challenges for 3D packaging.
Thermal management is a major issue in 3D package design (see "Beat the Heat With On-Chip Microfluidics," Drill Deeper 11178 at www.elecdesign.com). Air and heat flows, temperature distribution, system-level heat transfers, and natural and forced convection cooling all require parametric data that only the proper 3D EDA design tools can supply.
"Today's EDA tools are substantially better than those that existed a few years ago and continue to improve," says Carl Roberts, director of advanced packaging and Fellow at Analog Devices. He points out that designers can solve thermal design issues in 3D packages by looking more closely at the initial IC design approach. "A lot of thermal issues are rooted in how the chip design is implemented and how it is laid out," he adds.
Roberts was a key developer of the industry's first commercially available automotive microelectromechanical-system (MEMS) accelerometer. He believes that "Analog Devices' experience with MEMS technology makes it easier for the company to solve challenging 3D packaging problems, which it has been doing for quite some time."
Although SoC technology is deemed too expensive for lowcost consumer electronics packaging, efforts are under way to improve the SoC packaging cost factor—at least for now. Such is the goal of the Blue Whale Consortium, a project funded by the Information Society Technologies (IST) Programme of the European Community's Fifth Framework Programme.
Created in 2002, the Consortium's goal is to demonstrate wafer-scale packaging for RF SoCs and power devices, as well as to develop equipment for a waferballing process. Consortium members include the Netherlands' Philips Applied Technologies; Britain's DEK International; the Netherlands' Dimes, a subsidiary of the Delft University of Technology; Germany's Technical University of Berlin; and Israel's Shellcase Ltd.
David B. Tuckerman, senior VP and CTO for Tessera, foresees ongoing technology developments that will push product miniaturization even further. These include high-performance computing, wireless sensing, and image sensor processing (Fig. 7).
Jan King, senior vice president and technical marketing manager for Samsung Semiconductor, foresees the multistacked package (MSP) as the next evolution in 3D packaging for mobile applications. He expects MCPs and SiPs to be the forerunners of the MSP and believes that an MCP can produce a 70% space savings versus other packaging methods. In fact, an eight-chip MCP is under development at Samsung for the latest-generation 3G cell phones. It features the same thickness (1.4 mm) as its predecessor four-chip MCP and carries up to 3.2 Gbits of memory.
Although 3D packaging developments have met the challenges posed by consumerelectronics performance demands, packaging in the Z direction isn't always a clear-cut choice. A growing number of 3D-package suppliers points out that given the short product life cycles of one to two years for consumer electronics products,it may not always be feasible to go the 3D route. In fact, for some applications, plain old 2D planar technology often will suffice.
"You really need some combination of an SoC and an SiP approach where possible. All functions aren't created equal, so the appropriate packaging approach must be used," says Craig Mitchell, Tessera's VP of marketing.
One thing is certain. The move from wire-bonded interconnects to flip-chip or wafer-level packaging will accelerate. Future 3D packaging will use more wafer-to-wafer stacking as well as chipto-wafer stacking, with improvements and refinements in packaging costs, reliability, and form factor forthcoming.
"You need to be quick these days in trying to supply your customer's demands. Otherwise you lose the sale," says Analog Devices' Carl Roberts. "That means shorter design cycles, which adds pressure on both IC and package designers to get the job done right and on time."