Not many years ago, the only packaging issue that routinely concerned most chip designers was pin count. Package problems belonged to manufacturing, and designers were happy to "toss the project over the wall" once the prototypes had been tested successfully. Today, though, packaging is no longer an afterthought in chip design.
In the last few years, performance demands have changed rapidly, bringing lower voltages, increases in current, higher frequencies, and faster rise times to high-end digital and mixed-signal ICs (Fig. 1). Just as these factors modify the operation of the chip circuitry, they also alter the electrical requirements of the package. Designers who ignore these side effects in the package risk product failure.
In addition, rising package costs reflect the growing difficulty of keeping the package environment from interfering with chip operation. Multiple power and ground planes, and special routing and vias combine to raise the cost of the package as high as, or even higher, than the silicon it contains. Used appropriately, these features enhance the operation of the device, but they also serve to complicate the overall design picture.
Fortunately, package modeling tools have come a long way in recent years, providing designers with ways to evaluate the behavior of a chip within its package. Electrical models complement thermal and stress models to provide a complete picture of how the package will behave in operation. Together with models of the silicon circuitry, electrical package models can be fed into simulation tools such as Spice. Based on the results of simulation, a designer can change the chip layout or packaging features to ensure that the design works properly. Before going to the appropriate packaging house or vendor, however, a number of steps can be taken to facilitate the vendor-designer interface, to ensure a successful design.
The Package Environment
Although package modeling tools perform complex calculations, they cannot yet make critical design decisions. Therefore, the chip designer must understand how package characteristics can adversely affect a design. The designer can then tailor the chip for the package and make appropriate trade-offs to correct package problems that show up in simulation.
In a general way, a package behaves as a low-pass filter, because the RLC structure attenuates the voltage for fast changes in current (Fig. 2). So, at the very least, modeling tools must be able to predict the effects of resistance, inductance, and capacitance in the leads during worst-case chip operation. It is important to keep in mind that conductors within a package are not resistors, capacitors, and inductors in the sense of point features, but instead have distributed RLC properties along the length of the leads. Additional factors that may need modeling, depending on requirements, include lead impedance, signal timing, and the effects of energy dissipation throughout the package at high frequencies.
One of the axioms of package modeling is that a parametric value for a single lead indicates very little by itself. Any meaningful analysis must include coupling to all significant current paths, as well as any nearby signals that are potential sources of interference. Moreover, the model must be used in conjunction with simulation tools to provide a realistic picture of the package environment.
Package modeling considerations hold true for both mixed-signal and digital designs. Mixed-signal applications tend to use simpler packages with lower pin counts. They operate efficiently at high frequencies due to very short, low-inductance leads, and an abundant distribution of ground pins. Digital devices have generally required higher pin counts, increasing the complexity of the package, and, in some cases, requiring multiple-layered packages with ground (GND) and power (PWR) planes. As a result, each type of design receives a different emphasis during package modeling, though the overall concerns are the same.
In many designs, the overriding package problem is inductance, which is responsible for much of the voltage drop across leads. A significantly damaging effect of high inductance is ground bounce, in which the ground voltage level rises during rapid changes of current levels as the device operates. Power droop, in which the supply voltage (VSS) level falls, can occur as well. In both cases, inaccurate reference voltages can interfere with switching thresholds and cause bit errors, or restrict the operational range of signals.
The inductance of a lead considered in isolation (LSELF) depends largely on the section geometry and the length of the lead, though the latter relation is not linear. LSELF values must be combined with mutual inductance (LMUT) values among the signal paths to obtain the effective inductance (LEFF) when predicting the behavior of the package. LEFF reflects how the magnetic fields within the package behave as signals propagate through the circuit. Factored with the current change rate (di/dt), LEFF yields a voltage drop. Faster circuits, therefore, yield more voltage stability problems if LEFF remains the same.
Obviously, the challenge is to keep LEFF as low as possible, because rise times are likely to become faster and current levels higher in future designs. Physical isolation of conductors has a large effect on LMUT values, and thus on LEFF. All other things being equal, a pair of leads that are adjacent have higher LMUT values than a pair that are isolated.
To predict inductance effects accurately, the modeling software not only has to determine dynamic LEFF values for the leads, it also has to analyze how PWR and GND planes affect inductance in different areas. PWR and GND planes may serve to minimize overall LEFF in the package, especially in areas where they couple the current return paths to the signal lines. The software must be able to evaluate how local LEFF values are modified by the routing of signals, the placement of exit points for current sources and sinks, and irregularities such as holes in the plane for special structures.
The degree of accuracy required in calculating inductance is increasing rapidly, with LSELF values now commonly ranging from 1 to 10 nH per lead. However, current requirements for GND leads in some device families are headed toward 100 A in the near future, meaning that allowable LEFF values will drop into the picoHenry range. Accurate prediction of LMUT becomes very critical in these applications. When simulation reveals problems with inductance, designers can reduce LEFF by the proper coupling or separation of signals.
For example, several high-speed drives in a limited area of the chip might cause bounce in a single GND lead. The solution is often to populate the area with more GNDs to increase signal coupling into the GND system. These additional GNDs, of course, should have minimum coupling with one another, and should be interspersed among the other signal leads in the area. The modeling software will not only illustrate the problem, but also help the designer determine the optimal solution.
It would be advantageous to know what the maximum inductance values are for each type of package. Unfortunately, so many factors are involved that there's no way of reducing a package type to a specific value. Dual-in-line packages (DIPs) provide a good illustration of this point.
The longest leads in DIPs, with the highest LSELF values, are also isolated at the ends of the package, exhibiting low LMUT values. Thus, the LEFF values are high for circuits which use the end leads for currents that may be out of phase, such as PWR and GND. As a result, DIPs may perform poorly in high-frequency or high-current circuits. Nevertheless, some RF devices running at 2 GHz or higher are packaged in miniscule DIPs that control LEFF with scale and many GND leads. As these and other packages show, the overall inductance is strongly dependent on how the circuit operates, and the relative current paths in the package.
Historically, package types have been developed to move away from high LEFF. Radial packages, such as quad flatpacks, minimized the problems of standard DIPs by making all the leads nearly even in length. Unfortunately, the leads were still long, a problem that pin-grid arrays (PGAs) addressed with PWR and GND planes. However, the external PGA pins were narrow and perpendicular to GND planes, so they still had relatively high inductances*in some cases as high as the rest of the package.
As pin counts rose, designers were able to distribute signals more efficiently around the package, minimizing the LMUT problems that were classically characteristic of DIPs. Ball-grid arrays (BGAs) eliminated the PGA problem of pin inductance by eliminating the pins. Flip-chip mounting eliminated wire bonds, and could distribute bond pads across the surface of the chip.
Today, BGAs with flip-chip mounting and multiple PWR and GND layers normally represent the most efficient layouts, though for any given package, the LEFF values vary with chip size, signal coupling, and a number of other factors. Of course, higher pin counts also drive higher density and narrower conductor paths, exacerbating the inductance and coupling problems. And, so the battle continues.
In high-frequency designs, crosstalk between signals is often a key issue with the package. Due to mutual capacitance and inductance-coupling factors, active lines cause noise in adjacent lines, creating the potential for bit errors. Modeling with dynamic simulation can spot these problems and help determine the best remedy.
Generally, the design technique for minimizing crosstalk includes keeping inputs away from outputs. When critical signals are single-ended, they can be coupled with GND lines or planes, and moved farther apart for isolation. An effective solution to crosstalk is the use of differential signal paths, a technique designers employ more often in high-speed digital circuits. Here, the voltage difference between the two signals is detected, minimizing the effects of external noise sources.
When the impedance of a package lead does not match the impedance of the trace on the board, signal reflections can occur, causing unpredictable voltage levels until the reflection dissipates and the signal settles. To minimize the reflection problem and maximize the power transfer, a lead can be designed so that its characteristic impedance (ZCHAR) matches that of the driving source. The coupling of the signal to the return path is modified to set the value, with 50 Ω commonly requested.
ZCHAR is determined largely by geometric and spatial configuration, through material properties and the positioning of a lead relative to other leads, the planes, and other features. Modeling software makes it easier to perform this complex chore, and it can offer insight into the effectiveness of corresponding silicon structures that have been integrated to minimize reflections at the chip interface.
Scattering, Timing, And Losses
Microwave designers have long been accustomed to looking at scattering parameters, which measure the reflection and transfer of power throughout a structure. These reflections, and the signal interferences that they can cause, vary with changes in frequency. Scattering parameters will become increasingly important to digital designers as clock frequencies approach 1 GHz and beyond. The modeling and simulation software must be able to express the output in terms of these parameters.
In older devices, large output drivers exhibited relatively long time delays. Today's smaller output buffers have shorter delays at levels equivalent to the package delay. RC factors and time of flight, along with the intrinsic delay of electromagnetic propagation in the package medium, tend to slow down switching, and can prevent critical paths from fulfilling conditions. As frequencies increase, timing will be more of a packaging problem, as well as a device issue.
Another problem on the way is signal attenuation. Largely a matter of IR drops, attenuation has not mattered much to date. However, as voltage levels fall over time, voltage drops will have to be more closely controlled. Like scattering parameters, attenuation can be predicted using today's tools. Broader implications of timing are still being studied.
A suite of tools is generally used to calculate package-performance parameters. Boundary- and finite-element tools, field-energy-based algorithms, and partial-element equivalent-circuit (PEEC) methods are available to calculate parametric data for systems of conductors. Each tool uses somewhat different approaches to calculate capacitance, inductance, and resistance for the package environment.
Additionally, these methods can be applied in either 2D or 3D model development. The 2D applications yield inductance, capacitance, and possibly resistance per-unit-length data for a 2D cross-section of the conductor structure. The characteristic impedance can be calculated from the L and C data representing a typical cross-section.
A boundary-element-based program in 2D, for example, makes discrete elements of the surface (boundary) of the conductor. It calculates the charge distribution, assuming a known potential on each conductor, and that only surface currents exist. The total charge can then be calculated for each conductor, and the capacitance inferred from its definition as a ratio of the charge to potential difference. The inductance is usually calculated from the inverse of the C matrix, assuming unity dielectric.
This approach implies no currents internal to the conductors, and hence, no internal inductance (which is usually small for nonmagnetic conductors at frequencies typical of digital applications). Finite-element applications for 2D make discrete elements of the total cross-section. They can determine more information on current distribution over the lead cross section, and therefore, the internal inductance and resistance as a function of frequency. Note that the 2D applications assume a predefined current return path built into the inductance data.
The finite-element method may also be applied to 3D problems by using discrete volume elements. The PEEC approach, which uses discrete current filaments or paths, is also popular for 3D applications. These methods can supply information on the current distribution on planes and, thus, a full 3D picture of the inductance of all paths. The 3D tools allow the definition of current sources and sinks on the planes, giving the effects of these conditions on the operating characteristics of the package.
A more exhaustive analysis is performed by full-wave tools, which model how electromagnetic fields are propagated through the package structure. Because full-wave tools essentially solve a discrete form of Maxwell's equations; they are very thorough, but run relatively slowly. Even as computing power grows in the future, full-wave tools will continue to run slowly because the packages they model will become increasingly complex. At the same time, because they are so exhaustive in their analysis, full-wave tools provide high precision in the verification of other tools.
Chip designers must define certain basic information about the expected package electrical characteristics by supplying the knowledge they have about signal behavior, whether it's based on device simulation or previous designs. This information generally falls into two areas: power requirements and signaling specifications.
Power requirements include worst-case peak current levels, when all I/Os switch simultaneously, and rise times for core and output buffers. In addition, the chip designer needs to specify a noise budget showing how much noise is permissible in the PWR and GND at the chip. While zero noise is desirable, it is also unachievable, making the budget is an essential part of the package design.
These requirements allow the calculation of LEFF, which in advanced designs today, may be on the order of a few picohenries. LEFF, in turn, allows the package designer to determine how many PWR and GND paths are necessary, or whether PWR and GND planes are needed at all.
Important signaling specifications include how many single-ended and differential signals are required, and where they are located. High-speed signals may also require a GND plane to be specified for impedance control. In addition, the designer should specify how much isolation is required between inputs and outputs, defining how much crosstalk can be fed back to the inputs from the outputs. This crosstalk budget may be expressed as a percentage of the signal or in dB. Based on these specifications, the package designer can determine how much shielding to introduce through GND planes, and whether or not to isolate signals by relocating outputs.
Evaluating Vendor Support
Designers undertake complex digital or mixed-signal designs should be sure that the package vendors with whom they deal have access to a set of well-established, sophisticated tools that model the electrical, mechanical, and thermal characteristics of packages. Eventually, all of these models may operate together in a single integrated tool, but today the complexities of modeling make it very difficult to calculate electrical, mechanical, and thermal factors at the same time with the desired accuracy.
The electrical tools should include all pertinent paths in the model description. They also should take inputs directly from chip-design software and output them in a usable manner to simulation software such as Spice. At the minimum, the tools must be able to calculate RLC factors, with attenuation, timing, and scattering parameters at high frequencies as high priorities. Access to full-wave tools is also a desirable capability in the package vendor's tool chest.
Other factors can indicate how seriously the vendor views the electrical issues of packaging. Vendor participation in standards organizations such as JEDEC helps provide a common ground for package characterization throughout the industry. Vendors can also take part in industry efforts to improve package modeling tools. For instance, the Semiconductor Research Corp., Research Triangle Park, N.C. with funding and guidance from industry vendors, contributes to university research in package measurement and modeling. As a result, many of the best modeling tools come from research done in universities, notably the University of Arizona at Tucson.
Vendors must also dedicate resources to the extensive measurement and analysis required for model verification. Much of this verification is inferential, because the critical factors often cannot be measured directly. Texas Instruments, for instance, devotes an entire lab to this type of measurement to close the loop on the parametric information used in package models.
Ensuring Design Performance
Eventually, electrical modeling tools will be combined with layout tools to optimize the operation of the chip within its package automatically. However, until then, and even afterward to some extent, chip designers must be aware that the package is an electrical environment, and that their products can function more efficiently if they are designed with environmental factors taken into account. Package modeling software, combined with a good understanding of signal characteristics within the package, can help ensure that good designs perform as they should.