Electronic Design

SiP Packs High-Res Image Processing Into Tight Spaces

A new system-in-package (SiP) technology is capable of stacking logic and Gbit-class memory in a single package to enable high-speed, high-definition image processing in mobile devices. The technology, developed by NEC Corp. and its U.S subsidiary NEC Electronics, is called SMAFTI (SMArt connection with Feed-Through Interposer). It features a 3D chip connection with an approximately 60-µm gap and 50-µm-pitch microbump between the logic and memory devices, which can support transmissions up to 100 Gbits/s. Designers who use SMAFTI technology in cell phones and other size- and space-constrained portable equipment can achieve resolutions comparable to those achieved in high-definition television.

Most conventional SiP products have larger package sizes due to thicker interposers, and have limitations in signal transfer speed, wire-bonding interconnections, and side-by-side chip placement. NEC Electronics and NEC developed the SMAFTI technology by leveraging three key enabling technologies: a 50-µm-pitch microbump interconnection technology, a 15-µm-thick feed-through interposer (FTI) based on superconnect technology, and a multichip assembly process.

The microbump interconnection technology makes it possible to realize low power dissipation, a small form factor, and high-speed interchip communication at more than 100 Gbits/s, up to ten times faster than conventional technologies. The small 50-µm-pitch interconnection size is the result of a silicon-to- silicon attachment process that effectively reduces the size of conventional pitch bumps and enables designers to accommodate four times the number of bumps in the same area. This process produces high-speed data transfers and high reliability.

Superconnect technology is used in chip fabrication and has a copper signal trace 15 µm wide and a polyimide layer 7 µm thick, which is roughly half that of a conventional substrate. The 15-µm-thick FTI is based on superconnect technology, and makes it possible to convert a chip's wiring pitch to 50 µm and to fan out the pitch connection of an outer ball grid array to 500 µm. As a result, the routing of signals from a logic chip with a 50-µm pitch and memory connection points to universal substrate terminals can be simplified.

The multichip assembly process is an enhancement of existing wafer-based manufacturing processes that are typically used for SOC manufacturing. Memory chips are first mounted onto silicon wafers using wiring based on superconnect technology. Then the chips and wiring layer are molded by resin and the silicon wafer is removed. The BGA attachment process follows.

Products featuring SMAFTI technology are expected to be available during the first quarter of 2007 in a variety of lead-free package sizes. Availability is subject to change.

NEC Electronics
www.necel.com

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