The industry's first 90-nm test chip for X Architecture interconnect designs has been produced by Applied Materials (AMAT) at its Maydan Technology Center in Sunnyvale, Calif. The fabricated chip validates design rules and the manufacturability of X Architecture designs for copper/low-k chips using existing mask-making and wafer-processing technologies.
If you're not familiar with the X Architecture by now, you should be. It's a way of orienting on-chip interconnects using diagonal paths in addition to the traditional right-angle or Manhattan paths. The X Architecture has been shown to produce layouts with 20% less overall interconnect length or better and 30% fewer vias.
Test chips are critical to design-for-manufacturability efforts because they enable chipmakers to verify the quality and reliability of designs rules before mass production ensues.
The test chip produced at Applied Materials was the product of extensive collaboration. Cadence Design Systems supplied the test structure design and chip-validation tools. A Canon stepper was employed for wafer lithography. AMAT's interconnect fabrication technologies were used to produce the multilayer copper/low-k interconnect on 300-mm wafers. Results were confirmed using AMAT's wafer inspection and metrology systems to validate critical dimensions and defect levels.
The test-chip layout provided by Cadence included complex structures such as combs/serpents, interwoven mazes, via chains, line-width resistors, and 140-nm line/space geometries. No yield issues resulted, nor were there any show-stopping difficulties.
Previously, STMicroelectronics had reported good results with an X Architecture test chip at 130 nm. ST expressed confidence that it can manufacture X Architecture chips at minimum pitch in 130-nm design rules.
Cadence Design Systems