EDA Tool Synthesizes VLIW Hardware Architectures From Software
A|RT Designer lets designers use software to interactively develop hardware architectures. More specifically, it was designed for hardware equipment containing a VLIW-style controller and a variety of configurable datapath resources. These include ALUs, multipliers, adders, RAM, ROM, and registers.
The instrument's interactive and exploratory properties represent steps in the design flow between C code, running on a processor, and the generation of an optimized HDL implementation. It also gives designers complete control over the allocation, assignment, and scheduling of hardware resources. In addition, the architecture can be modified to optimize performance, silicon area, or power consumption.
Other features include cross highlighting between all views and a built-in pragma editor with extensive help utilities. The latter allows designers to add or remove specific datapath resources, assign particular operations to certain resources, or alter the scheduling of operations according to different strategies.
There are two versions of the A|RT Designer architectural synthesis tool: A|RT Designer and A|RT Designer Pro. Both are available for HP-UX, Sun Solaris, and Windows NT platforms. Prices start at $65,000 per seat.
Frontier Design, Abdijstraat 34, 3001 Leuven, Belgium; +32 16 39 14 11; fax +32 16 40 60 76; www.frontierd.com.
System Design Debugger Receives Productivity Upgrade
By improving and automating the design debugging process, the Debussy system increases electronic circuit and systems designer productivity. The system's 4.4 version enhances the debugging capabilities of the original. Bugs in complex or unfamiliar designs are resolved more quickly, making engineers even more efficient.
Version 4.4 adds support for the Linux operating system. This gives users new platform choices for debugging to coincide with the growing number of Linux verification tools. Support for NT and UNIX platforms is offered as well. The upgraded system also boasts automatic debugging features, which make it possible to instantly locate and isolate problem logic. Other benefits include improved state coverage analysis as well as greater Verilog and VHDL simulator support. In addition, the new version advances Debussy's support of VHDL language constructs.
Debussy 4.4 for Windows NT, Unix, and Linux platforms is now shipping. Modules range in price from $3000 to $10,000. Users with maintenance contracts will receive a platform-independent version of 4.4 without any additional cost.
Novas Software Inc., 2025 Gateway Pl., Suite 480, San Jose, CA 95110; (888) NOVAS-38, (408) 467-7888; fax (408) 467-7889; www.novas.com.
Silicon And Software Performance Enhanced By Design Software
Version 9.5 of the MAX+PLUS II programmable logic development software features a compilation engine optimized for the FLEX 10K device family. This makes it possible for customers with designs targeting such devices to experience more than a 30% improvement in design performance. It also allows them to achieve compilation times that are up to 30 times faster than before. The timing models for the EPF10K30E and EPF10K50S have been updated in this design software to reflect silicon process improvements. These process upgrades create faster parts, which in turn increase customer system bandwidth.
All users on the company's active subscription and maintenance plan can now receive the MAX+PLUS II version 9.5 software. With a $2000 single-user license, customers also are entitled to Quartus development tools and a year's worth of software updates.
Altera Corp., 101 Innovation Dr., San Jose, CA 95134; (408) 544-7000; www.altera.com.
Capture And Management Tool Increases Productivity
Renoir 99.5 is an enhanced HDL design, capture, and management environment for ASIC and FPGA design. Compared to previous editions, it features automatic layout functionality, advanced design documentation capabilities, and improved design management. These upgrades provide greater design consistency and reusability, as well as improved ease of use and productivity for time-critical system-on-a-chip (SoC) applications.
The HDL2Graphics feature now comes with a diagram layout and autorouting algorithm that automatically creates compact easy-to-read block diagrams from complex HDL code. The enhanced Block Diagram editor and Design Browser provide a graphical notation known as Frames for "conditional and repetitive instancing." It's also easier to display and share information generated in Renoir. Additionally, a document export function complements the existing print capabilities to support object linking and embedding.
Starting at $6000, Renoir 99.5 is immediately available on Solaris, HP-UX, and Windows 95/98/NT. A free evaluation version is available at the company's web site.
Mentor Graphics Corp., 8005 S.W. Boeckman Rd., Wilsonville, OR 97070-7777; (503) 685-1214; www.mentor.com.
Software Development Kit Aids In High-Volume SoC Applications
The SDK 2.0 software development kit has been added to the ManArray DSP product family. This latest version provides the tools necessary to develop high-performance, scalable and reusable DSP cores for high-volume system-on-a-chip (SoC) applications. It also allows customers to easily convert C, C++, and MATLAB files into ManArray assembly code for their DSP applications.
Containing an integrated development environment, SDK 2.0 offers a system simulator, instruction set simulator (ISS), and a compiler for MATLAB and Vector libraries. The kit also includes a GNU-C compiler, assembler, linker and loader, VLIW packer, register allocator, DSP libraries, and ManArray technical information and coding examples.
SDK 2.0 is available for a free evaluation period for PC and UNIX operating systems. Price depends on the options selected.
BOPS Inc., 101 University Ave., Suite 410, Palo Alto, CA 94301; (650) 330-8400; fax (650) 330-1086; www.bops.com.