Electronic Design

PC-Controlled Current Source Supplies 100-V, 1-A, 16-Bit Pulses

The current source shown in the figure is designed to support toroidal-cavity nuclear-magnetic-resonance electrophoresis (TCNMRE) measurements of molecular electrical mobility in chemical samples. To do so, it generates (via PC programming and NMR spectrometer triggering) sequences of precise (16-bit), bipolar, high-current (up to 1 A at 100 V) pulses. The current source therefore em-bodies a number of design ideas of potential utility in ATE and other programmable-power-supply applications as well as in TCNMRE applications.

The current source incorporates a PC-controlled, optoisolated, 16-bit digital-to-analog converter (DAC) described in an earlier IFD ("16-Bit PWM Optoisolated DAC Is PC-Controlled," Aug. 20, 2001, p. 83). As explained there, the 16-bit PWM conversion waveform comes from the relative phase of the 500-Hz square-wave outputs of two 16-bit ripple-carry counters (comprising U4-U7), free-running from a common 30-MHz RC clock (U3B). This phase is determined by the initial values loaded into the counters before the clock is enabled as well as the states of PC port bits D5 and D6. Depending on this phase, the duty cycle of the 1-kHz output of exclusive-OR U2C can be varied linearly from 0% to 100% in increments of 0.0015% (1/216).

The PWM waveform is then split into two complementary drive signals by CMOS switch U1A and applied to the LEDs and their optically coupled, inverted (i.e., VCE < 0) phototransistors of optoisolators U9AB. The dc component is extracted by the three-pole, 14-Hz, unity-gain, U10A low-pass filter. Output ripple of the filter is at the sub-16-bit level. The filter's settling time for 16-bit (0.0015%) accuracy is approximately 0.1 s.

The 16-bit 0- to 5-V output of U10A is input to the switched, precision 1-A current source comprising U10B, MOSFET Q5, and opto-switch U9C. The current source is disabled when U9C is held in conduction by U3C and is enabled when U9C turns off. When enabled, U10B forces Q7's gate terminal to the forward bias required to make the voltage developed by the 5-Ω sense resistor, RS, match the 0- to 5-V U10A DAC voltage. While the voltage compliance of the current source is large (more than 100 V), it is, of course, finite. The loss of current regulation due to voltage limits is signaled by Q7's saturation and the consequent rise of its gate terminal voltage to 15 V. This turns off Q2, Q1, the U9D opto, and thereby the "NOOV" overvoltage error bit in the parallel interface.

Although the source's peak power output capability is large (>100 W), the duty cycle and average power output required for TCNMRE are limited by the lack of tolerance of sample heating and are quite low (<10% and 10 W). In pursuit of economy, the maximum average output power capability of the source is designed to be comparably low. The danger of overheat damage therefore exists if the DAC is programmed for a high output current and the GATE input is hit with a high-duty-cycle signal. U1C, U8, U3C, and U9C act to detect any occurrence of excessive duty cycles and to react by disabling the output circuitry (via U9C). The PC is notified of the error condition via status bit 5 ("dutok" = "duty cycle okay") in the parallel interface.

Control of output-current polarity is handled by two electromechanical relays controlled by port output bits 0 and 1. Two bits and two SPDT relays, rather than one bit and one DPDT relay, were used as a safety measure. A non-zero current-source output can occur only when the control bits are in opposite states. Therefore, after power-up initialization when the bits are in the same state, the source's output is effectively disabled. This configuration eliminates a potential shock hazard. The relatively slow pulse rate of TCNMRE prevents the slow actuation speed of mechanical relays from being problematic.

Another safety feature built into this current source is provision for rapid (<<1 s) discharge of the large and potentially hazardous CV2/2 energy (~50 J) stored in the filter caps on power-down. This is accomplished by arranging the unused contacts of the power switch so as to establish a discharge circuit through the power transformer primary when turned off.

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