256-Mbit DDR SDRAMs Deliver 2.1-GB/s Bandwidth

Sept. 1, 1999
A means of doubling the bandwidth of main memory is available in the firm’s 256-Mbit, double-data-rate (DDR) synchronous DRAMs. The HM5425xxx SRAMs provide 2.1-Gbyte/s bandwidths when used with a 64-bit bus. They conform to JEDEC standards and

A means of doubling the bandwidth of main memory is available in the firm’s 256-Mbit, double-data-rate (DDR) synchronous DRAMs. The HM5425xxx SRAMs provide 2.1-Gbyte/s bandwidths when used with a 64-bit bus. They conform to JEDEC standards and offer an easy transition path from traditional SDRAM chips, it’s claimed.To achieve their high speeds and bandwidths, the 133-MHz DDR SDRAMs perform read and write operations on both edges of the clock. The 256-Mbit memories also have four banks of data storage cells that operate simultaneously and independently. An integrated delay locked loop aligns the output data with the input clock for reliable data transfers. To ease integration, the chips use a standard JEDEC SSTL-2 interface and come in a 400-mil, 66-pin TSOP.

Company: HITACHI SEMICONDUCTOR AMERICA INC.

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