9-Mbit Sync SRAMs Eliminate Dead Cycles

With this new family of 9-Mbit synchronous SRAMs, data can be transferred on every clock cycle, enabling random read or write operations. Dead cycles are eliminated, thus increasing bandwidth and enhancing bus throughput in any given system topology. The memories, which are known as NtRAMs, are suited for communication and networking system applications where speed and available bandwidth are critical to system performance. The initial lineup includes 150-, 143- and 133-MHz pipeline burst NtRAM and 83- and 75-MHz flow-through burst NtRAM devices. The 150-MHz pipeline version features 3.8-ns access times and the 83-MHz flow-through version, 9 ns. All operate from one 3.3V supply and support both 3.3V and 2.5V I/O. The memories come in 100-pin LQFPs and support Snooze mode by ZZ pin control and Byte Write control. Samples are available.