Memory system design for system-on-a-chip (SoC) ASICs is not a simple task. Optimizing memory access is challenging and design choices can significantly impact performance and power requirements. Memory subsystems typically provide basic services such as blocks of memory or single port caching. These days multicore environments often with asysmmetric processor architectures are common. Targeting these with a unified memory is very challenging.
Memoir Systems has developed a multiport caching system called Algorithmic Memory (Fig. 1) that is designed to deliver a 10x increase in memory operations per second (MOPS). Algorithmic Memory is more than just a caching system. It is designed to be a front end for any existing memory technology and is tailored for multiport operation in embedded designs where multiple devices need access to shared memory. It can double the throughput of the memory while incurring only a 15% overhead.
Memoir Systems can be a front end for more than one kind and speed of memory. Typically a SoC is designed with different memory technologies such as DRAM and static RAM. Memoir Systems approach allows these to be integrated into a single design providing higher performance memory access in a unified addressing scheme. This can be challenging for SoC designers where the memory architecture is a custom design.
Memoir Systems' design approach takes into account the various memory parameters such as row size and bank layout. The Memoir Systems' design tool provides designers with a menu of options to specify the back end memories and the devices that need to access memory. This includes details like the number of read and write interfaces, the clock frequency of the subsystems, and special requirements like chip layout and power optimizations. This configures the RTL IP (intellectual property) that is the core the the Algorithmic Memory design. The Memoir Systems' approach significantly reduces the design process time. The RTL IP does not target a physical platform allowing Memoir’s technology to be process, node and foundry independent.