The SigmaRAM Consortium has announced the first availability of JEDEC-standard high-speed 18-Mbit synchronous SRAMs tailored to the networking and telecom markets. These devices can sustain a data throughput rate of up to 24 Gb/s at a 333 MHz clock speed. They come in two architectural flavors: common I/O and separate I/O. The former features a 72-bit shared data bus, while the latter has independently optimized, 36-bit, read and write buses. Both variations offer DDR architectures that can sustain similar throughput with fewer pins. SigmaRAM devices employ a 209-pin BGA package for scalability from 18-Mbit to 144-Mbit densities and ease in routing. Additional features include low-power consumption resulting from a 1.8V supply voltage and JEDEC-standard 1.5V and 1.8V interfaces. Sampling of the 18-Mbit SigmaRAM devices is scheduled for Q4 2001. For more information on the SigmaRAM Consortium, please visit its web site.
Company: SigmaRAM Consortium
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