Electronic Design
Cranking Up Serial Memory Speeds for In-Place Execution

Cranking Up Serial Memory Speeds for In-Place Execution

Fig. 11. Adesto’s eXecute-in-Place (XiP) storage can reduce overall system complexity and cost.


Serial memory provides a low-cost, low-pin-count solution that is ideal for low-cost, low-power mobile applications, such as wearable devices and other connected solutions in the Internet of Things (IoT). Adesto’s latest serial memory delivers high performance eXecute-in-Place (XiP) storage for types of applications. The XiP approach can reduce system complexity and cost (Fig. 1).

Of course, there is a trade-off with serial memories: performance. While using fewer signals reduces the throughput, protocol overhead and bus size are also major factors. Simple serial peripheral interface (SPI) devices use a single serial channel. Quad SPI (QPI or QSPI) moves four data bits at a time using seven pins while Octal SPI (OPI) moves eight data bits using only 11 pins. All use significantly fewer pins than a parallel memory interface. There are single (SDR) and double data rate (DDR) implementations that can also affect performance.

Fig. 22. Adesto’s cache oriented fetching retrieves the requested byte first so an application can continue, but it then delivers the rest of the cache line followed by the first part of the cache line. Subsequent reads retrieve the next set of sequential cache data without the need to send more commands or addresses. (Click image to enlarge)


In addition, Adesto has provided a protocol designed to work with processors that have a cache associated with the system. The protocol optimizes the fetching of a 16-byte cache line instead of a single byte (Fig. 2) that is usually delivered in response to a command and an address. This can significantly reduce overhead.

Using only one command and address for one or more cache lines can significantly improve performance (Fig. 3). This provides a 41% speed-up for the processor without changing the clock frequency of the memory. This is a common burst mode technique, with the main difference that the first line of data is ordered based on the initial address.

Fig. 33. Adesto’s protocol uses a single command and address per block, and subsequent blocks can be read without an additional command. (Click image to enlarge)


The combination of features allows a 133-MHz device to provide a throughput of 156 Mbyte/s with a latency of only 57ns. This assumes a 16-byte cache line and an average of 3.84 cache line fetches per cache miss. There are versions available that operate at 200 MHz.

Adesto’s memory incorporates additional features like a split memory bank. Having two memory partitions allows one to be used for writing while fetching application code from the other. This allows over the air (OTA) updates with a single memory device. Granularity is 1/8th of the memory array. Another feature is auto power down mode and the ability to complete a write while the host is powered down.

Fig. 44. EcoXiP provides better throughput, up to 156 Mbytes/s with a 133 MHz clock, and lower latency (57 ns) than more conventional approaches.


Developers can take advantage of the OPI mode alone with many existing chips. Taking advantage of the more advanced support, such as cache line loading, requires compatible processor chips. Adesto is working with microcontroller vendors to make this happen.  Ultimately, this could result in substantial power savings and improved system performance.

TAGS: Mobile
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