Electronic Design

Generator Delivers Multiport Embedded Memory Designs

Memoir Systems announced their Algorithmic memory awhile ago but its use required a custom design (see Algorithmic Memory Simplifies SoC Memory Subsystem Design). The idea was to take standard single port memory solutions and generate a multiport solution by adding extra logic between devices and memory. The Algorithmic memory approach is quite broad allowing multiple memory types to be combined.

Memoir's Renaissance design tool (Fig. 1) targets a common subset of Algorithmic memory, dual port SRAM. A designer simply provide a single port memory and the tool generates a dual port front end based on the designer's specification. This approach significantly reduces development time while meeting the necessary performance requirements.


Figure 1. Mix specs and a single port SRAM and Renaissance generates the desired dual port design.

A 6 transistor (6T) cell is used to implement the typical SRAM cell. This is noted as 6T-RW. A dual port cell can be built using 8 transitors or 8T-2RW. There are variants but essentially each requires a different design.

Memoir's Renaissance design tool targets four different dual port types (Fig. 2) including 2RW, 1R1W, 1RW1W and 2Ror1W. These are utilized in different applications from caches to lookup tables. This allows a designer to choose the optimum architecture while minimizing overhead.


Figure 2. Memoir's Renaissance targets four types of dual port memory.

There are a number of reasons developers may want to choose Memoir's approach. First, dual port solutions provide a unified memory view that typically simplifies the implementation and programming chores. The alternative is often having different blocks of memory for different jobs requiring paritioning decisions as well as making programming more complex. Second, 8T-2RW designs tend to be more complex, require more space and use more power that 6T-RW designs and Memoir's combined solution (Fig. 3). Finally there is a design process is significantly shorter and less costly.

Creating and verifying memory compiler takes a good bit of time and lots of money. The compiler allows designers to generate arrays of memory cells. Each design requires about the same amount of each so it will only be done if there is sufficient demand. Single port memory is the most commonly used design so memory vendors may not choose to design the gamut of solutions especially if designers can utilize a tool like Renaissance.


Figure 3. Memoir's two port design power requirements have a similar growth rate to single port solutions while the 2RW approach spikes up over 400 MHz.

Even two port cell designs have challenges as clock rates rise (Fig. 4). They also require more power.


Figure 4. Memoir's two port solutions maintain their density improvement over 8T-RW designs.

The Renaissance tool incorporates application optimizers to reduce overhead, size and power requirementes for a particular application. It can handle arrays up to 16 Mbits requiring only a standard SRAM interface. It can lower power and size requires versus an 8T solution by up to 50% with up to 30% clock frequency increase.

It is possible to replicate the job that Renaissance does but it would take time and then there is the issue of support. Memoir's approach is to deliver that design for a price but one that would be significantly less than doing it from scratch allowing designers to get a solution out the door quicker. Dual port memory designs can now take days and deliver a selectable level of performance.

TAGS: Digital ICs
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